應力對具自我對準栓塞式閘極結構之新穎閘極環繞式多晶矽奈米通道搭配抬升式源極/汲極薄膜電晶體影響之研究

近年來由於元件結構持續的微縮，電晶體的性能在超大型積體電路的製作上已變成巨大的挑戰，短通道效應在通道長度急速微縮的情況下變得十分嚴重。於是，尋找新的結構來取代傳統的平面電晶體結構對於下個世代的半導體技術來說，成為了無法避免的課題。特別是當通道長度來到了數十奈米時，嚴重的短通道效應將會產生許多問題，因此良好的閘極控制能力將扮演十分重要的角色。多重閘極結構比平面閘極結構提供了更優越的靜電控制能力，因此能更有效地控制通道，減少通道在奈米尺度下的短通道效應，因此環繞式閘極奈米線電晶體是下個半導體科技世代中最具潛力的候選人之一。近年來有越來越多的消費性電子產品製造商，將可撓式面板運用在各式各樣的電子產品上，像是電子紙、行動電話等等。為了達到這樣的需求，可撓式面板上的周邊電路應用將變得不可或缺。然而，對於機械應力在奈米線通道電晶體上的影響，在過去的研究文獻中並沒有被廣泛地報告。在這份論文中，我們將對直徑10奈米以下的奈米線通道電晶體，研究在外加應力影響下，奈米線通道電晶體的電性變化。

關鍵字

應力；奈米線電晶體；閘極環繞

並列摘要

Recently, due to aggressive scaling of device structures in MOSFETs technology, the performance of MOSFETs has become a huge challenge in ultra large scale integrated (ULSI) fabrication. The control of short channel effect (SCE) becomes crucial owing to the shrinking of gate length. Therefore, the seeking of novel structures to replace traditional planar MOSFETs is essential for the next generation technology node. Because of the significant short channel effect, the excellent gate control ability of device plays an important role in the gate length on the order of atomic dimensions. The multiple-gate architectures have electrostatic advantages over traditional planar devices. The additional dimensions of the gate provide better gate control ability, and therefore reduce the short channel effect. Consequently, GAA (Gate-All-Around) nanowire transistors are the most promising advanced architecture candidates for the next generation technology node. In recent years, there has been considerable attention from numerous consumer electronics manufacturers to apply flexible display in electronic paper, mobile phones and other consumer electronics. Because the demand for flexible consumer electronics is increasing, flexible peripheral circuits are needed. However, the impacts of mechanical stress on extremely small scale device, such as sub-10-nm GAA nanowire FETs has been rarely addressed in the previous reports. In this thesis, we describe a study of characteristics of drain current and threshold voltage of sub-10-nm GAA nanowire FETs under externally applied mechanical stress.

並列關鍵字

Strain ； NW TFTs ； GAA

參考文獻

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[11] J. Chen, T. Saraya, and T. Hiramoto, “Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range,” in VLSI Symp. Tech. Dig., pp. 175–176, 2010.

國際替代計量

應力對具自我對準栓塞式閘極結構之新穎閘極環繞式多晶矽奈米通道搭配抬升式源極/汲極薄膜電晶體影響之研究

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