In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how many should we place hardware process monitors. The proposed guide line for on-chip hardware process monitors placement shows better efficiency than greedy method. The mean error and maximum error is reduced over 50% in different parameter of process variation. A comparison of different method of speed binning is also presented. ii