多重閘極無接面金氧半場效應電晶體之物理，元件操作，及電路應用之研究

Physics, device operation, and circuit application of multi-gate junctionless metal-oxide-semiconductor field-effect-transistors

韓銘鴻(Ming-Hung Han)

指導教授 ： 張俊彥

國立交通大學/電機學院/電子工程系所/博士(2013年)

https://doi.org/10.6842/NCTU.2013.00528

摘要

本論文詳細的探討了多重閘極無接面金氧半場效應電晶體的物理原理，元件操作方式，以及其在積體電路中應用的可能性。本文主要共分成三大方向，第一部分是探討無接面電晶體與一般傳統的金氧半場效應電晶體在物理特性上的不同。在本文中，藉由能帶圖的分析以及電子濃度分佈的模擬，我們發現了無接面電晶體的電流在導通時不同於一般傳統型電晶體這樣集中於通道表面，而是在整個半導體內部流通。這樣的導通機制可避免載子在導通時遇到高電場劣化以及表面散射之不良效應，但同時我們也發現這樣的導通機制相較於一般傳統型電晶體，對於閘極電壓有著較緩慢的反應，使得導通電流值較小。由於無接面電晶體使用高濃度的通道摻雜，載子移動時之散射機制由雜質離子散射為主，因此載子遷移率對於溫度效應也不同於一般傳統型電晶體，造成在一般電晶體中常見的汲極電流零溫度係數效應點也不存在於無接面電晶體中。在無接面電晶體中，由於通道和源極汲極的摻雜濃度沒有差異，因此通道中之電荷僅由閘極所控制，不會有源極汲極和通道接面之干擾，因此在元件關閉時，因受閘極電場影響，等效通道長度會大於閘極物理長度，這樣的特性使得無接面電晶體對於短通道效應具有較好的控制能力，而且可以降低閘極對源極汲極重疊區之寄生電容。一般無接面電晶體導通時操作在平帶區，這使得其導通時的閘極電容值小於一般傳統型電晶體導通時操作在強反轉區之電容，但也造成其對於溫度之效應較為敏感。本文的第二部份則是對使用單晶矽基板及玻璃基板兩種技術的無接面電晶體在元件直流及交流特性，製程之便利性，以及在積體電路中運用之可行性做比較。在使用單晶矽基板的技術中，由於我們在基板使用了反型態的摻雜，這使得載子在導通時受限於通道及基板接面的影響，而會集中於通道中間偏上方來流動。這樣的效果將有助於閘極對載子移動的控制，使得短通道效應和小訊號輸出導納變好，但這樣也同時使得載子導通的面積變小，造成導通電流和轉導的下降以及串連電阻的上升。若考慮製程的便利性，我們發現使用單晶矽基板技術的無接面電晶體具有以下幾個優勢:第一，它和目前工業界標準的多重閘極傳統型電晶體的製程方式匹配，便於量產;第二，相較於玻璃基板的無接面電晶體，其對於製程變易造成的元件特性偏移有較佳的抵抗力;第三，它多了可以使用基板濃度這個參數來調整元件特性。但若比較元件電容及高頻特性，本研究發現通道及基板接面會額外造成較大的寄生基板電容，因此使用單晶矽基板技術反而是不利的。在電路應用方面，本文所提出的兩種無接面電晶體均能有效的操作於反向器及靜態隨機存取記憶體電路中，但相較之下，使用玻璃基板的技術，具有較快的反應時間以及較小的功率消耗，而且甚至可以操作在外加偏壓僅0.25V的情況下，這對於未來如手機等低功率消耗的應用是一大利多。本文最後一部分，我們成功的製作出了通道厚度僅2奈米的無接面薄膜電晶體，其具有理想的次臨界擺幅值和高達十的八次方的開關電流比。另外，本研究亦發現其崩潰電壓達到五十伏，遠高於類似尺寸的傳統型薄膜電晶體以及在高壓應用下常用的橫向擴散金氧半場效應電晶體，而這主要歸功於無接面電晶體的結構本質像一個電阻，使得電場可以均勻的分佈在整個半導體區域內，而非一般的傳統型電晶體只集中在通道汲極的接面之上。因此無接面電晶體對於高壓元件的應用也是具有潛力的。

關鍵字

三維元件模擬 ； 無接面電晶體 ； 金氧半場效應電晶體 ； 奈米科技

並列摘要

In this work, we comprehensively study the physics, device operation, and applications of the multi-gate junctionless (JL) metal-oxide-semiconductor field- effect-transistor (MOSFET). In the first part of this work, we discuss the physics difference between JL transistors and conventional inversion-mode (IM) multi-gate transistors. The bulk conduction of the current in JL transistors has been addressed by the band-diagram and distributions of carrier density. Such conduction mechanism prevents the carrier mobility suffering from high field degradation and surface scattering, but shows a weak dependence on the gate bias. In JL transistor, since the dominating scattering mechanism is the impurity scattering due to heavily doped channel is used, the temperature dependency of the drain current is differ from IM transistor, the zero temperature coefficient point is not observed. Owing to the doping concentration gradient between source/drain and channel is zero, the depletion charge is control by the gate alone, the effective channel length is larger than gate length when JL transistor is turned off, resulting in the better short channel effect control and smaller total gate capacitance due to the reduction of gate to source/drain overlap capacitance. The JL transistor usually operate at flat-band condition when device is turned on, the total gate capacitance is smaller than that in IM transistor, but it also obtain a larger variation with the change of temperature. In the second part of this work, we compare the performance of JL transistor with bulk and silicon-on-insulator (SOI) substrate and study their advantages and limitations. In JL bulk transistor, the carriers concentrate on the top side of the channel due to the channel/substrate junction reduces the effective channel thickness. Such phenomenon improves the control of short channel effect but degrades the on-current simultaneously, and results in a better output conductance but a worse transconductance than those of JL SOI transistor. The JL bulk transistor performs less sensitivity to the device process variation, and provides an additional design parameter, substrate doping concentration, to tune the device performance. For analog and radio frequency characteristics, JL bulk transistor shows worse performance than in JL SOI transistor because of the parasitic substrate capacitance. The JL SOI transistors performs a shorter delay time, a smaller power consumption, and a larger static noise margin than those of the JL bulk transistor in the analysis of inverter and static random access memory (SRAM) circuits, and the JL SOI SRAM can operate at a very low supply voltage, which is benefit to the digital circuit application. In the last part of this work, we successfully fabricate a JL thin-film-transistor (TFT) with 2nm-thick channel; the measurement results demonstrate a 108 on/off current and a 61mV/dec subthrshold swing and are robust to process variation. We also measure the breakdown voltage of such device and compare it to IM TFT and laterally-diffused-metal-oxide-semiconductor (LDMOS). Our JL TFT obtains much higher breakdown voltage because the electric field in the device is uniformly distributed liked a resistor, indicating the potential of high-voltage application.

並列關鍵字

3D Simulation ； Junctionless ； MOSFET ； Nanotechnology

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