In this thesis, we propose a self-aligned T-gate scheme and have successfully demonstrated it in the fabrication of ZnO TFTs. The T-shaped gate assists the formation of source/drain metal and sidewall air spacers in a self-aligned manner, which is beneficial for reducing the parasitic capacitance/resistance components. The completed devices exhibits good switching behavior, but anomalously high series source/drain resistances are identified which significantly degrade the device characteristics. Possible root causes for this phenomenon are discussed in this thesis. We also study the effects of annealing, plasma treatment, the shape of gate, and gate dielectric material on the performance of T-gate devices. The Vth shows a positive shift after the annealing in oxygen ambience accompanied with increases in field-effect mobility and on/off ratio. The plasma treatments are found to be able to dramatically change the channel properties such as increasing or decreasing the conductivity of the channel, depending on the kind of plasmas being used.