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  • 學位論文

P型SONOS快閃記憶體元件電荷動態分佈之研究

Exploring Trapped Charge Evolution in P-Channel

指導教授 : 渡邊浩志

摘要


在此篇論文中,我們研究了P型SONOS記憶體元件藉由通道熱電洞引發熱電子(CHHIHE) 動態寫入機制(dynamic programming) 。採用三維元件模擬,對SONOS中因動態寫入機制儲存於氮化矽的電子分佈進行研究。我們發現藉由通道熱電洞引發熱電子動態寫入機制,通道熱電子注入點從汲極延伸至源極,造成儲存於氮化矽的電子分佈在短暫的寫入時間內,展延至整個氮化矽層,顯示通道熱電子在P型SONOS記憶體元件可以均勻注入並儲存。此特性不同於N型SONOS記憶體元件,電子被局部束縛於氮化矽層。

並列摘要


In this thesis, the trapped charge evolution in SiN layer by dynamic programming (PGM) of Channel Hot Hole Induced Hot Electron injection (CHHIHE) is precisely investigated in p-channel SONOS memory device. 3D device simulation is calibrated by comparing the measured PGM characteristics. It is found, for the first time, that the CHHIHE injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. The injected charges quickly spread over on the almost whole channel area uniformly during a short dynamic PGM period, which will afford large tolerance against lateral trapped charge diffusion by baking. This characteristic is different from the case of n-channel SONOS, where injected charges are locally concentrated near to drain side.

參考文獻


[1] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi,“NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 543–545, Nov. 2000.
[2] L. Avital, A. Padovani, L. Larcher, I. Bloom, R. Arie, P. Pavan, and B. Eitan, “Temperature monitor: A new tool to profile charge distribution in NROM memory devices,” in Proc. IEEE Int. Rel. Phys. Symp., pp. 534–540, Mar 2006.
[3] A. Shappir et al., “Spatial characterization of localized charge trapping and charge redistribution in the NROM device,” Solid State Electron., vol. 48, 2004, pp. 1489-1495.
[4] E. Nowak, E. Vianello, L. Perniola, M. Bocquet, G. Molas, R. Kies, M. Gely, G. Ghibaudo, B. De Salvo, G. Reimbold, and F. Boulanger “Charge Localization during Program and Retention in Nitrided Read Only Memory-Like Nonvolatile Memory Devices,” J. Appl. Phys., vol. 49, 2010.
[5] A. Padovani, L. Larcher, P. Pavan, L. Avital, I. Bloom, and B. Eitan,“ID– VGS-Based Tools to Profile Charge Distributions on NROM Memory Devices,” IEEE Trans. Device Mater. Reliab., vol. 7, no. 1, pp. 97–104, Mar. 2007.

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