單晶三維積體之銦鎵砷/鍺超薄電晶體邏輯電路與靜態隨機存取記憶體考慮層間電耦合之分析

Analysis of Monolithic 3D Logic Circuits and 6T SRAM using Ultra-Thin-Body InGaAs/Ge MOSFETs considering Interlayer Coupling

余冠瑾(Kuan-Chin Yu)

指導教授 ： 蘇彬

國立交通大學/電機學院/電子工程系所/碩士(2015年)

https://doi.org/10.6842/NCTU.2015.00361

摘要

本論文中，我們研究了單片三維層間電耦合對銦鎵砷/鍺邏輯電路與6T靜態隨機存取記憶體的影響。本論文比較了三維與二維的結果，亦比較了銦鎵砷/鍺與矽的結果。此外，本論文研究了單片三維層間電耦合對6T靜態隨機存取記憶體在不同臨界電壓設計的影響，並利用銦鎵砷/鍺材料取代矽材料來進一步提升其性能。
TCAD模擬結果指出單片三維銦鎵砷/鍺反向器與非及閘透過最佳化佈局，可以在維持與二維電路相同漏電流的情況下改善性能。單片三維銦鎵砷/鍺6T靜態隨機存取記憶體透過最佳化佈局，可以在維持與二維電路相同漏電流的情況下同時改善穩定性與單元性能。本論文也分別針對6T靜態隨機存取記憶體在高效能與低功耗的操作模式提出建議的三維佈局。此外，邏輯電路與6T靜態隨機存取記憶體從二維到三維電路的性能改善，銦鎵砷/鍺相較於矽的改善更多。
對於不同臨界電壓設計的矽6T靜態隨機存取記憶體，單片三維結構可以擴大高臨界電壓設計的RSNM的優勢以及縮小高低臨界電壓設計的單元性能差距。此外，對於高效能的操作模式，互補式金氧半導體利用銦鎵砷/鍺取代矽可進一步改善6T靜態隨機存取記憶體的單元性能。單片三維銦鎵砷/鍺具高臨界電壓設計的6T靜態隨機存取記憶體可以在維持與矽的相對應電路有差不多的RSNM的情況下同時改善單元性能與WSNM。

關鍵字

單晶三維 ； 銦鎵砷/鍺 ； 邏輯電路 ； 靜態隨機存取記憶體 ； 層間電耦合

並列摘要

This thesis investigates monolithic 3D logic circuits and 6T SRAM composed of InGaAs-n/Ge-p MOSFETs considering interlayer coupling. We have compared the 3D results with the 2D counterparts, and have compared the InGaAs/Ge results with the Si counterparts. In addition, we have investigated the impact of interlayer coupling for 3D 6T SRAM with high/low threshold voltage design, and have shown enhanced performance by replacing Si CMOS with InGaAs/Ge CMOS.
TCAD simulation results indicate that monolithic 3D InGaAs/Ge inverter and 2-way NAND can improve the performance while maintaining equal leakage with 2D counterparts through optimized layouts. Similarly, 3D InGaAs/Ge 6T SRAM can simultaneously improve the stability and cell performance while maintaining equal leakage with 2D counterparts through optimized layouts. We have also suggested two layouts for 3D 6T SRAM for high performance and low power operation, respectively. Moreover, compared with the Si counterparts, InGaAs/Ge logic circuits and 6T SRAM cell exhibit larger performance enhancement of 3D over 2D designs.
For Si 6T SRAM with different threshold voltage (VT) designs, monolithic 3D structure can enlarge the RSNM advantage of high VT design and reduce the gap in cell performance between high/low VT designs. Moreover, replacing Si CMOS with InGaAs/Ge CMOS can improve the 6T SRAM cell performance. Monolithic 3D InGaAs/Ge high VT SRAM can improve the cell performance and WSNM while maintaining comparable RSNM as compared with the Si counterparts.

並列關鍵字

Monolithic 3D ； InGaAs/Ge ； Logic Circuits ； 6T SRAM ； Interlayer Coupling

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