低溫沉積之介電層與三維堆疊垂直閘極結構運用於電荷儲存式快閃記憶體之特性研究

Effect of Low-Temperature Formed Dielectrics and Vertical Gate 3D Stacked Junctionless Charge Trapping Flash Memory Devices

陳柏皓

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/碩士(2015年)

摘要

近在元件日漸微縮的趨勢下，平面式元件微縮空間有限，造成元件密度難增加且製程難度跟著大幅的提升，因此如何提升電性又能提高元件密度為目前最重要的課題之一。有些解決方法已漸漸被提出，如高介電常數材料的應用、奈米線通道的結構、無接面快閃記憶體元件的應用和三維堆疊陣列等等。本篇論文以三維可堆疊式電荷捕捉式快閃記憶體元件為主軸，輔以高介電常數材料作能帶工程的應用，目的是用三維結構增加單位面積之元件密度，並且用二氧化鉿/氮化矽堆疊的電荷捕捉層優化其特性。
第一個實驗首次做出我們自己設計的三維垂直式堆疊閘極和無接面通道結合應用在快閃記憶體元件上。本實驗中，以傳統的氧氮氧(ONO)結構為記憶體的氧化層，製作在無接面奈米線通道式的快閃記憶體元件上，因為是堆疊閘極元件，所以做出的快閃記憶體元件有上下兩層，我們將兩層的特性做比較。因為是無接面元件，在寫入速度和可靠度特性的表現上都具有不錯的表現，唯抹除速度較為緩慢，而在上下層元件的一致性和互相干擾特性都算良好。
第二個實驗中以二氧化鉿/氮化矽堆疊的結構作為電荷捕捉層，製作在第一個實驗一樣的結構上但沒有做堆疊閘極，期望使用能帶工程的電荷捕捉層達道改進抹除速度的效果。用上了二氧化鉿/氮化矽堆疊電荷捕捉層，不管是在寫入速度和元件可靠度上都比第一章更加的提升，且在最在意的抹除速度方面也能達到預期有所提升，故能帶工程的結果對此元件的特性是有幫助的。
第三個實驗目的在於找尋低溫的氮化矽層來源，以達到減低熱預算的目的。此章與第二章使用相同的電荷捕捉層，分為能帶工程堆疊和單層電荷捕捉層，唯一的差別是裡面的氮化矽層，使用較低溫的感應耦合電漿化學氣相沉積(ICPCVD)，用此機台沉積的氮化矽薄膜當作電荷儲存層，製作在反轉式的奈米線快閃記憶體元件上，並與常見較高溫的低壓化學氣相沉積(LPCVD)之氮化矽電荷捕捉層元件做比較。結果發現兩機台沉積出的薄膜，因為元素中成分的不同而造成元件表現特性也有不同，ICP沉積的元件在寫抹特性上有較優良的表現；而LPCVD沉積的元件有較好的電荷保持力。不管哪種沉積方式，堆疊式的電荷捕捉層也能對各種電性表現有改善的效果。

關鍵字

低溫沉積介電層 ； 垂直閘極三維堆疊記憶體 ； 無接面電荷捕捉記憶體 ； 能帶工程

並列摘要

The scale down of flash device is limited by its micro-miniature planar devices, which makes the process flow more complex. How to improve the electrical characteristics and increase the device density at the same time becomes two of the most important issues. Some approaches have been reported such as the BE-SONOS, nanowire channel structure, junctionless (JL) channel and 3D array flash memory devices. In this thesis, a 3D stacked structure is implemented in charge trapping (CT) flash memory devices with high-k stacks to increase device density. Besides, the performance can be improved by HfO2/Si3N4 stacked trapping layers.
In the first study, a CT flash device with stackable vertical gate structure is demonstrated for 3D memory integration. It is found that the program/erase (P/E) speeds and reliability of top and bottom devices are similar. Small program disturb and large disturb-free window are achieved. However, a conventional SONOS dielectric layer is used on JL channel flash memory devices. The erasing speed is still an issue and it need to be improved.
In the second study, the HfO2/Si3N4 stacked trapping layers are implemented on the same vertical gate structure as the first study. We want to know if the stacked trapping layers can improve the erasing performance on this device. The results show that the devices exhibit better programming speed and reliability. Besides, erasing speed becomes faster by using bandgap engineering trapping layers.
In the last study, although HfO2/Si3N4 stacked trapping layer plays an important role on flash memory, its thermal cycle in fabrication process may induce the degradation of trapping layers in 3D structure devices. To reduce thermal cycle, a low-temperature formed Si3N4 is used to replace the conventional one. The low-temperature formed Si3N4 is deposited by inductively coupled plasma chemical vapor deposition (ICPCVD), and a high-temperature formed one is conventionally deposited by a low pressure chemical vapor deposition (LPCVD). From the energy-dispersive spectroscopy, the compositions of Si3N4 layers are different, result in that P/E speed of ICP sample is faster than that of LPCVD one. Besides, LPCVD sample has better retention than ICP one.

並列關鍵字

Low-Temperature Formed Dielectrics ； Vertical Gate 3D Stacked Flash Memory Devices ； Junctionless Charge Trapping Flash Memory Devices ； Bandgap Engineering

參考文獻

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