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  • 學位論文

應用於三維反及閘式快閃記憶體之逆電流式感測及分層式溫度補償電路

Reverse Current Sensing with Layer-aware Temperature compensation for 3D BE-SONOS TFT NAND Flash Memory

指導教授 : 張孟凡

摘要


近來,大容量資料儲存裝置的廣泛運用造就了反及閘式快閃記憶體無可取代的地位。憑藉著比其他平面半導體記憶體還小的元件面積,反及閘式快閃記憶體掌握了高元件密度以及低製造成本的優勢。 隨著科技的發展,現在最先進的反及閘式快閃記憶體已經微縮到小於二十奈米的等級。然而,製程微縮使得平面半導體的製造越來越困難。最糟的是,因製造困難而上升的成本甚至會比製程微縮所減少的成本還多。為了同時降低成本以及增加記憶體容量,三維反及閘式快閃記憶體應運而生。 由於架構上的限制,反及閘式快閃記憶體的隨機讀取速度十分緩慢。因此,反及閘式快閃記憶體必須以平行讀取來同時輸出大量資料以增加它的市場競爭力。 我們提出一種應用於三維垂直閘極 BE-SONOS 型式反及閘快閃記憶體的逆電流式感測及分層式溫度補償電路。這種逆電流式感測方式可以支援資料平行輸出,並且不受源極線上以及位元線耦合的雜訊影響。此外,此逆電流式感測專用的分層式溫度補償電路可以使之在 -40~125 ̊C下維持一定的資料可靠性。

並列摘要


Nowadays, the wide-spread usage of the large data storage devices contributes to the indispensable status of the NAND Flash memory. With the smallest cell area among the 2D memories, NAND Flash memory holds the superiority in cell density and cost. The state-of-the-art 2D NAND Flash memory has reached 1X nanometer node. However, the technology scaling makes the fabrication of NAND Flash much more difficult than before. Worst of all, the cost caused by the fabrication difficulty even exceed the cost saved by the shrinking cell size. In order to reduce the bit cost while increasing the storage capacity at the same time, the 3D NAND Flash technology is developed. Due to the structural limitation, the random access speed of NAND Flash memory is quite slow. As a result, the parallel sensing to simultaneously read out a large amount of data is essential to enhance the competitive capability of it. We proposed a reverse current sensing scheme for 3DVG BE-SONOS NAND Flash memory with the layer-aware temperature compensation capability. It can support the parallel read to enlarge the data throughput; in addition, the proposed sensing scheme is totally immune to the source line noise and the BL cross-talk noise. Furthermore, the layer-aware temperature compensation can effectively maintain the reliability of the reverse current sensing at -40~125 ̊C.

參考文獻


[2] F. Masuoka, M. Momodomi, Y. Iwata and R. Shirota, “New ultra high density EPROM and flash EEPROM with NAND structure cell,” International Electron Devices Meeting Technical Digest, pp. 552-555, Dec. 1987.
[3] T. Tanaka et al., “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” Symposia on VLSI Circuits Digest of Technical Papers, pp. 105-106, Jun. 1990.
[5] K. D. Suh et. al., “A 3.3V 32Mb NAND Flash memory with Incremental Step Pulse Programming Scheme,” International Solid-State Circuits Conference Digest of Technical Papers, pp. 128–129, Feb. 1995.
[6] J. K. Kim, K. Sakui el al., “A 120 mm2 64 Mb NAND flash memory achieving 180 ns/byte effective program speed,” Symposium on VLSI Circuits Digest of Technical Papers, pp.168-169, Jun. 1996.
[7] K.-T. Park et al., “A 3.3 V 128 Mb multi-level NAND Flash memory for mass storage applications,” International Solid-State Circuits Conference Digest of Technical Papers, pp. 32–33, Feb. 1996.

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