能帶工程介電層、複晶奈米線通道與無接面設計應用在三維電荷儲存式快閃記憶體之特性研究

Effects of Bandgap-engineered Dielectrics, Polycrystalline Nanowire Channel and Junctionless Configuration on 3D Charge-trapping Flash Memory Devices

諶俊元(Chun-Yuan Chen)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/博士(2014年)

https://doi.org/10.6843/NTHU.2014.00609

摘要

複晶(polycrystalline)快閃記憶體近來被研究應用在三維(three-dimensional, 3D)NAND記憶體堆疊上。為了改善其電性與微縮，各種方式如非晶矽結晶、奈米線(nanowire, NW)通道結構以及能帶工程(bandgap engineering, BE)等皆被提出。在本論文中，我們首先探討由(低溫)富氮性(N-rich)氮化矽/二氧化矽所構成的堆疊式穿隧層對快閃記憶體電容造成的效應，應用此能帶工程穿隧層的元件，其寫入與抹除速度皆較單層穿隧層元件要高，但電荷保存力會稍微的下降。接著，我們研究氧化鉿/氮化矽堆疊形成的能帶工程式電荷儲存在複晶矽(polycrystalline silicon, poly-Si)快閃記憶體上的效應，發現此能帶工程式電荷儲存層在奈米線通道元件上能顯著提升記憶體元件的寫入抹除速度與電荷保持力。在第三個研究中我們將氧化鉿/氮化矽堆疊式電荷儲存層同時應用到無接面式(junctionless, JL)元件與反轉式(inversion mode, IM)快閃記憶體元件上，無接面元件不僅是寫入速度、電荷保持力與元件耐寫抹特性都比反轉式元件好，抹除速度也因氧化鉿/氮化矽儲存層的應用而改善到可與反轉式元件的相比擬。
除了能帶工程與無接面設計在複晶矽記憶體元件上的應用之外，我們也研究了矽鍺掩埋式通道(SiGe buried channel)在複晶矽上的應用，在複晶矽奈米線上磊晶矽鍺掩埋式通道有效提升了元件的寫入抹除速度與元件耐寫抹特性同時不減損電荷保持的能力。我們更提出了將複晶鍺(polycrystalline germanium, poly-Ge)奈米線應用於快閃記憶體元件上，複晶鍺因為自然摻雜的特性讓它在低溫又簡單的製程下就能完成無接面元件的製作，這樣的製程條件使複晶鍺無接面元件很適合用在三維記憶體微縮，電性的表現上也與一般所提出的複晶矽元件相近。
在最後一個研究中，我們實現一個可堆疊式的垂直閘極快閃記憶體，我們發現上下兩個元件有相近的寫入抹除速度以及可靠度的表現，在絕緣氧化層厚度為50奈米時，元件之間的寫入干擾很小，干擾免疫的記憶窗變化不大，因此這個結構很適合用來與能帶工程和不同通道材料整合應用。

關鍵字

快閃記憶體 ； 能帶工程 ； 複晶奈米線通道 ； 無接面設計

並列摘要

Polycrystalline channel flash memory device has been studied for the application of three-dimensional (3D) NAND integration. For better device characteristics and continuous scaling, any methods have been proposed such as α-Si crystallization, nanowire (NW) channel and bandgap-engineered (BE) dielectrics. In this dissertation, effects of BE tunneling layer composed of nitrogen-rich (N-rich) SiN/SiO2 and low temperature (LT) N-rich SiN/ SiO2 stack are investigated on bulk capacitor device first. Devices with BE tunneling layer show faster programming and erasing (P/E) speeds but a little degraded retention performance. In the next study, a BE trapping layer composed of HfO2/SiN (HN) stack is applied to polycrystalline silicon (poly-Si) devices with planar and NW channel. Compared with the SiN trapping layer device, P/E speeds are improved by HN stacked trapping layer and the improvement is more effective on NW channel device. The retention performance of devices is also improved because of the lower conduction band level of HfO2. In the third study, HN stacked trapping layer is applied on both inversion-mode (IM) and junctionless-mode (JL) poly-Si flash device. With HN stacked trapping layer, JL device performs faster programming speed and comparable erasing speed with that of IM one, which is rarely seen in reported works which apply SiN as trapping layer and present slower erasing speed of JL device. Retention and endurance performances of JL device are also better than those of IM one.
Apart from the applications of BE and JL configuration on poly-Si flash device, characteristics of poly-Si device with SiGe buried channel are also studied. P/E speeds and endurance performance are improved by SiGe buried channel without degrading the retention performance. In the next study, pure polycrystalline germanium (poly-Ge) JL flash memory device is proposed for lower fabrication temperature and complexity. The JL configuration is formed by the naturally p-type doping of poly-Ge film such that no additional implantation and activation are needed. Good operation characteristics are also observed. In the final study, a stackable vertical gate structure is demonstrated for 3D memory integration. It is found that the P/E speeds and reliability performances of top and bottom devices are similar. Small program disturb and large disturb-free window are observed with the 50-nm thick SiN isolation layer. The 3D stackable structure is also compatible for the integration with BE and different polycrystalline channel.

並列關鍵字

flash memory device ； bandgap engineering ； polycrystalline nanowire channel ； junctionless transistor

參考文獻

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