應用於三維反及閘式快閃記憶體之分層寫入驗證以及溫度補償位元線嵌位電路設計

Layer Aware Temperature Compensated Bit Line-clamp Generator for 3D BE-SONOS TFT NAND FLASH Memory

徐若瑜

指導教授 ： 張孟凡

國立清華大學/電機資訊學院/電子工程研究所/碩士(2014年)

摘要

在現今的半導體記憶體中，反及閘式快閃記憶體在大容量資料存取的應用中扮演非常重要的角色。由於元件面積是平面半導體記憶體中最小的，反及閘式快閃記憶體可以達成相當高的元件密度並且降低製造成本。為了研發更優質的產品，如何繼續增加密度、降低成本就顯得非常重要。現今最先進的反及閘式快閃記憶體已經微縮至二十奈米，平面式的反及閘式快閃記憶體微縮越來越困難，成本越來越高。既然無法縮小平面上的元件，要達成更高記憶體容量的另一個辦法就是在垂直方向堆疊更多的元件。在這樣的概念下，三維的反及閘式快閃記憶體應運而生，目前被視為下一世代大容量資料存取應用的解決方案。
不同於平面式的記憶體環境單純，在三維反及閘式快閃記憶體中，不同堆疊層具有些微的製程差異。也因此，不同堆疊層的初始臨界電壓值分布以及對於溫度產生漂移的係數也各不相同。假如我們使用相同的寫入驗證電壓去驗證所有的堆疊層，將會造成反及閘式快閃記憶體單元的耐久力下降。
我們提出一款位元線嵌位電路設計，搭配反向感測機制，即可滿足各層所需的寫入驗證電壓以及溫度補償。此款電路可以儲存多筆資料，資料內容為目標層與參考堆疊層之間的初始臨界電壓差加上目標層的溫度補償電壓。最後將這些電壓同時傳送至各自頁面緩衝器的位元線嵌位電晶體。傳統的溫度補償方式是將補償電壓加於字元線上，然而三維垂直閘架構中的字元線供應電壓給所有的堆疊層，因此無法延用。我們所提出的電路能根據個別堆疊層提供不同補償電壓能大大改善操作的精準度以及記憶體的耐久度。

關鍵字

三維及閘式快閃記憶體 ； 位元線嵌位 ； 分層寫入驗證 ； 分層溫度補償

並列摘要

In the modern semiconductor memory, NAND flash plays an important role to data storage. It can achieve high cell density and low cost with the smallest cell area in the planar semiconductor memory. To develop up-to-date product, increasing the density and decreasing the bit cost have turned into the top target. The state-of-the-art of modern NAND flash technology has reached 2X nanometer. The technology scaling has become more and more difficult and expensive. In order to conquer the restriction, the three dimensional (3D) NAND flash technology has been regarded as the solution of the next generation large data storage application in the recent year.
The three dimensional (3D) differs from the planar NAND flash memory; each layer has their unique environment. Hence the initial VTH distribution and the temperature coefficient are different from the other layers as well. The endurance of NAND flash cell will degrade if we keep applying the same program verification voltage to all layers.
To reach the goal of layer aware program verification and temperature compensation, we proposed a Bit-Line-clamp (BL-clamp) Generator that should be used with reverse sensing scheme. This proposed circuit can storage several datas that contains the initial VTH difference between target and reference layer combine with the temperature compensated voltage for target layer. And then transferring these datas to the Bit-Line-clamp transistors of each page buffer (PB) simultaneously. In the conventional way, the temperature compensated voltage is applying to the WL. However, each WL is connected to all layers in the three dimensional vertical gate (3DVG) structure. This proposed circuit offers the different compensated voltage to each layer will greatly improve the accuracy and memory endurance.

並列關鍵字

3D NAND flash memory ； Bit Line-clamp ； Layer Aware Program Verification ； Layer Aware Temperature Compensated

參考文獻

Fujio Masuoka, M. Momodomi, Y. Iwata and R. Shirota, “New ultra high density EPROM and flash EEPROM with NAND structure cell,” in Int. Electron Devices Meeting (IEDM), vol. 33, pp. 552-555, 1987.

H.Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 14-15, June 2007.

Hang-Ting Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, pp. 547-550, Dec. 2005.

Hang-Ting Lue et al., “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 131-132, June 2010.

Rich Liu, H. Lue, K.C. Chen, and C. Lu, “Reliability of Barrier Engineered Charge Trapping Devices for Sub-30nm NAND Flash,” in Int. Electron Devices Meeting (IEDM), pp. 1-4, Dec. 2009.