自我組裝關鍵技術應用於三維積體電路研究

隨著莫爾定律的極限，製程技術的微縮已無法有效益地提昇積體電路的效能。為了解決此技術瓶頸，利用垂直堆疊的三維積體電路技術也被視為解決方法。而三維積體電路的關鍵技術之一的接合技術是由晶圓對晶圓的對接(wafer to wafer)及晶片對晶圓的對接(chip to chip)兩種堆疊方式組成，由於晶圓對晶圓的堆疊仍有晶片良率不足(known good dies, KGD) 不足的問題，會導致整體構裝之良率無法改善。所以晶片對晶圓的堆疊方式被視為解決良率的最佳方式，可藉由KGD的挑選，提高整體構裝的良率。此外，良率是以精準的對準為基準，精確的對準才能使元件的功能做運作。不過隨著現在電子元件或光電元件尺寸微縮，數量也大幅度的增加，傳統的對準方式跟構裝抓放的方式已不甚經濟，所以新的一套具經濟且有效的對準方法近年來已受到重視，而利用自我組裝的技術具有快速增加大量的產出受到矚目，所以我們利用材料間的親水性(hydrophilic)與疏水性(hydrophobic)兩種極大差異的表面張力去設計自我組裝機制。此機制透過許多材料分析去找出屬於自我組裝材料的最佳品質與參數，進而應用於此研究已達到最佳的效益，此外，亦透過檢測對準誤差值去驗證此機制在對準方法的應用性。所以最後的成果就是將此自我組裝概念應用於對準的方法不只可以保持原本晶片與晶圓堆疊具有堆疊KGD於控制良率的特色，且透過精準度的量測發現此機制具有在不失精準度基礎及低成本的控制下大幅度增加產出，此外亦可以應用在接合技術以因應現況。

關鍵字

三維積體電路；自我組裝；親疏水表面張力；晶圓對疊方式；晶圓接合

並列摘要

With facing the limit of Moore’s law, the semiconductor technologies no longer satisfy and promote the efficacy of integrated circuits (IC). Three-dimensional integrated circuits (3DIC) is regarded as the solution in order to breakthrough the bottle-neck of semiconductor technology by vertical stacking. The characteristic of vertical stacking which replaces the two dimensional transportation have some benefits such as small form factor, high performance, high throughput, low power consumption, hetero-integration and low RC delay. Bonding, a key technology of 3D integration, is stacking approach including wafer-to-wafer (W2W) and chip-to-wafer (C2W). Wafer-to-wafer bonding has the issue of confirming known good dies (KGDs), which directly influence the yield of whole packaging. Therefore, for solving this problem, chip-to-wafer (C2W) bonding can be regarded as the solution to KGD issue. This method improves the yield of whole packaging by picking known good dies (KGD). In addition, the yield of stacking is based on high precision alignment. Only a precise alignment method can make the device favorably work. However, with the scaling size and large amounts of electronic devices, traditional alignment and pick-place are plagued by the inefficiency and high cost. The self-assembly technology has a potential of developing rapid production. In this thesis, hydrophilicity and hydrophobicity of the surface tension are adopted to design the self-assembly function to be applied in the alignment method. This method possesses low cost, high precision, stacking KGD in mass package and high throughput. After the process is successfully developed, the quality of self-assembled monolayers (SAMs) directly determines the performance of self-assembly. The SAM quality is dependent on the experimental parameters such as dip-coating time and heating time. Finally, the self-assembly is observed and satisfies the requirement of high throughput and low cost. According to the misalignment measurement results, this design is shown with a high precision alignment and can be totally applied with bonding technology.

並列關鍵字

3DIC ； Self-assembly ； Self-assembled monolayers ； SAM ； Hydrophilic/Hydrophobic ； 3D stacking ； Bonding technology

參考文獻

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自我組裝關鍵技術應用於三維積體電路研究

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