基於射頻互聯之三維動態記憶體多核移動平台的應用驅動記憶體分配

隨著技術的發展，下一代行動裝置應該具備處理更高畫質影像解析度的能力。這就需要下一代行動裝置的記憶體存取頻寬和存儲容量得到提升以用來處理例如三維立體高畫質影像或者畫中畫這樣龐大的影像資料。然而傳統的隨機存取記憶體由於引腳數量的約束不能有效提升存取頻寬。現在已有的解決方案是利用矽導孔(TSV s)技術的三維動態記憶體堆疊，這種方案比傳統的隨機存取記憶體多出至少32倍的引腳。更進一步的方案是在三維動態記憶體堆疊的基礎上，結合射頻互聯的技術來進一步大幅提高記憶體的存取頻寬。這種方案的頻寬比單純的矽導孔(TSV s)技術的三維動態記憶體堆疊多出4倍（信道被分為4種頻率的傳輸通道）在本論文中，我們將評估這種新的記憶體架構與之前的傳統隨機存取記憶體架構還有三維動態記憶體堆疊的架構的系統性能。我們會構建不同的系統架構，來分析他們的頻寬和功耗，以這兩點為參考來比較不同系統架構的系統性能。

關鍵字

射頻互聯；記憶體分配；三維動態記憶體堆疊

並列摘要

The next generation of mobile devices should have the ability to deal with higher resolution of high definition (HD) video than nowadays mobile devices with the development of technology. High memory bandwidth and large memory capability are required for these mass video contents such like three-dimensional high definition video or picture in picture. However, conventional DRAMs fail to increase memory bandwidth by the limit of I/O pins. The through-silicon-vias (TSVs) in 3D-stacked DRAM is a valuable solution up to now, the number of I/O pins are 32x at least compared to conventional DRAMs. A further solution is based on radio frequency interconnect (RFI) in 3D-stacked DRAM to further substantial increase memory access bandwidth. The bandwidth will be 4 x compared to the TSVs 3D-stacked DRAM when it has 4 carriers. In this paper, we will evaluate system performance of this new memory architecture by comparing it with the previous conventional memory architecture as well as TSVs 3D-stacked DRAM. Different system architecture will be built to analyze their bandwidth and power consumption, these two points as a reference to compare their system performance.

並列關鍵字

RFI-Based ； Memory Allocation ； 3D-Stacked DRAM

參考文獻

[1] John L. Hennessy, David A. Patterson, “Computer Architecture A Quantitative Approach Fifth Edition, ” 2012.

[2] B. H. Jeonget et al., “A 1.35 V 4.3 GB/s 1 Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application,” ISSCC, pp. 132–133, 2009.

[5] JEDEC Wide I/O 2 Standard document, JESD229-2, AUGUST 2014.

[6] Weiliang Yuan, Chuen Khiang Wang, Zheng Boyu, “Electrical Performance Evaluation & Comparison of High-Speed Multiple-Chip 3D Packages,” Electronics Packaging Technology Conference, pp.114-119, 2010.

[7] T. Whipple, T. Kukal, K. Felton, and V. Gerousis, “IC-Package Co-design and Analysis for 3D-IC Designs,” 3D Systems Integration Conference (3DIC), pp.1-6, 2009.

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基於射頻互聯之三維動態記憶體多核移動平台的應用驅動記憶體分配

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