金屬誘發側向結晶複晶矽P型多晶矽薄膜電晶體的元件特性及熱載子效應研究

在本篇論文中，我們利用一種新穎的測試結構，來分析P型金屬誘發側向結晶複晶矽薄膜電晶體(MILC-TFT)的通道結晶品質、以及可靠度問題。藉由量測此獨特電晶體的基本電性，我們便可以了解通道中特定位置的結晶品質對電性的直接關聯。藉由此結構，我們能夠很容易地分析元件的對稱(SSW)、非對稱引洞(ASW)等組態、以及通道長度(L)對於基本電性的影響，這些不同的引洞位置、以及不同的通道長度的組合將可能產生較差的薄膜品質，例如在長通道下(L > 5 μm)將有固相結晶(SPC)晶粒的出現，而在某個通道長度的範圍裡(L = 2~5 μm)，對稱引洞元件的通道中間會產生許多缺陷，這些較差的結晶品質將導致元件特性變差。另一方面，有了此特殊結構的幫助，我們便能夠深入解析熱載子造成元件局部地區的衰退。我們發現當元件操作於在較大的閘極與汲極間的壓降時，更多的電子將會注入閘極氧化層，進而導致元件更快速的衰退。值得一提的是，這些電 ii 性的變化顯示出熱載子將會嚴重的損害MILC-TFT閘極氧化層，而導致大量的電子被閘極氧化層捕捉。這傷害於固相結晶薄膜電晶體(SPC-TFT)比較輕微，然而SPC-TFT的主要衰退則是由通道中額外形成的缺陷所引起，此缺陷是由於通道裡的弱鍵被熱載子打斷而產生的。

關鍵字

金屬誘發側向結晶複晶；矽薄膜電晶體；可靠度

並列摘要

In this study, we have fabricated a novel test structure to analyze the effects of location-dependent film crystallinity and reliability issues in p-channel MILC TFTs. By using this unique structure, impacts of the film crystallinity on device characteristics can be directly analyzed by the measurement of transfer characteristics on the monitor transistors embedded in the test structure. Moreover, it is convenient to address the impacts of asymmetry seeding window (ASW) and symmetry seeding window (SSW) configurations as well as the channel length (L) on device performance. The generation of inferior film crystallinity in the poly-Si, such as the SPC granular structure or defect rich region, is closely related to the seeding window arrangement and the channel dimensions. The SPC granular structure mainly degrades devices characteristics of ASW devices with L > 5 μm, while the impacts of the existence of defect-rich region on SSW devices are peaked at L = 2~5 μm. iv With the help of the novel test transistors, the location-dependent damage can be resolved by measuring the degradation of subthreshold characteristics of monitor transistors. We found that major degradation arises from the electron injection in the gate oxide as drain bias is large and the voltage difference between the gate and drain is significant. It is worth to mention that the MILC devices under hot carrier stress suffer more from the electron trapping in the gate insulator. However, the SPC devices are more vulnerable to the generation of additional trap sites in the channel due to the abundance of weak bonds which are easily struck and broken by energetic carriers.

並列關鍵字

Metal Induced Laterally Crystallization ； TFTs ； Realiability

參考文獻

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[3] N. Ibaraki, “Low-temperature poly-Si TFT technology,” SID Intl Symp Digest Tech Papers, pp. 172-175, 1999.

[5] M. Aoki, T. Hashimoto, T. Yamanaka, and T. Nagano, “Large 1/f noise in polysilicon TFT loads and its effects on the stability of SRAM cells,” Jpn. J. Appl. Phys., vol. 35, pp. 838-841, 1996.

[6] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, pp. 1930-1936, 1996. [7] F. J. Gutierrez, L. Ares, J. I. Robla, M. C. Horrillo, and I. Sayago, “Properties of polycrystalline gas sensors based on DC and AC electrical measurements,” Sensors and Actuators Chemical, vol. 8, pp. 231-235, 1992. [8] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and

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金屬誘發側向結晶複晶矽P型多晶矽薄膜電晶體的元件特性及熱載子效應研究

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