使用I-Line雙重曝光技術實現非對稱0.1μm P型金氧半場效電晶體與相關可靠度問題之研究

A Study of Double-Patterning Technique with i-line Stepper to accomplish 0.1μm PMOSFETs and Its Related Reliability Issues

張博翔(Po-Hisang Chang)

指導教授 ： 林鴻志 ； 黃調元

國立交通大學/電機學院/電子工程系所/碩士(2010年)

https://doi.org/10.6842/NCTU.2010.01044

摘要

本篇論文使用i-line光學步進機，應用雙重微影成像法之技術，製作出遠優於i-line光學步進機解析度極限(~0.3μm) 的次0.1微米的閘極圖形;並搭配新設計的光罩，改進先前研究遭遇到元件過度蝕刻造成缺陷的問題[1]。這技術包含了兩次光學微影以及後續蝕刻製程。此技術可應用在非對稱金氧半場效電晶體的結構設計與製作，其電晶體可以比傳統的對稱結構有更大的最佳化空間。本研究調變了汲極延伸區域的接面深度與源極/汲極邊緣的局部摻雜（halo implant），來驗證其對於驅動電流、短通道效應的影響，最後再進行元件負偏壓溫度不穩定性的分析研究。

關鍵字

i-line光學步進機 ； 雙重微影成像法 ； 非對稱P型金氧半場效電晶體 ； 局部摻雜 ； 源極/汲極延伸區域 ； 負偏壓溫度不穩定性

並列摘要

In this thesis, we developed a novel double patterning technique, which consists of two exposures with an i-line stepper and two etch steps, to define poly-Si gates with line width down to sub-100nm regime, far beyond the resolution limit of the conventional i-line lithographic method (~0.3 μm). The double patterning process has also been employed in fabrication of sub-100 nm p-channel devices. During the course, we addressed an unexpected etch-induced recess phenomenon encountered in the study of our group in previous year [1] with ingenious modification in the mask design. We’ve also demonstrated the capability of the developed double patterning method in fabricating MOSFETs with asymmetrical S/D. The basic electrical characteristics of the PMOSFET devices with symmetrical and asymmetrical S/D were measured and compared. The results confirm the enhancement of immunity to the short-channel effects with asymmetrical S/D design. Finally, we also explored the negative-bias-temperature-instability (NBTI) of the fabricated devices.

並列關鍵字

i-line stepper ； double patterning technique ； asymmetric PMOSFETs ； halo implant ； S/D extension ； negative-bias-temperature-instability (NBTI)

參考文獻

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