利用雙重微影成像法製作非對稱N型金氧半場效電晶體之元件特性研究

A Study on the Device Characteristics of Asymmetric NMOSFETs with Double-Patterning Technique

簡敏峰(Min-Feng Jian)

指導教授 ： 林鴻志 ； 黃調元

國立交通大學/電機學院/電子工程系所/碩士(2010年)

https://doi.org/10.6842/NCTU.2010.00411

摘要

在本篇論文中，我們發展出一種新穎的雙重微影成像技術，利用I射線光學步進機，成功製作出100奈米閘極圖形的N型金氧半場效電晶體。這方法包含了兩次光學微影，以及蝕刻製程來形成閘極圖形。雖然製程較傳統標準作法複雜，但可以避免一般製程中的繞射效應，藉此突破I射線光學微影方法的解析度極限，達到100奈米甚至更細的線寬。此外，此製程更可以用來製作非對稱的元件。在本篇論文中，我們調變了非對稱源極/汲極的暈邊(halo)大傾角佈植條件，並分析出大傾角佈植對於元件基本特性，熱載子退化效應和低頻雜訊所造成的影響。
我們發現大傾角佈植可以有效減少漏電流以及改善短通道效應，可是大傾角佈植卻會導致更嚴重的逆短通道效應和降低驅動電流。對可靠度而言，由於大傾角佈植會增加在閘極邊緣下的側向電場強度，進而使熱載子退化效應變得更嚴重。在非對稱元件運用上，在源極端的大傾角佈植可以改善熱載子可靠度，此現象可歸因於靠近汲極端較小的側向電場.
最後，我們探討大傾角佈植對低頻雜訊之影響。當通道越短時，由於大傾角佈植會造成臨界電壓不均勻的分佈，故導致低頻雜訊劣化

關鍵字

非對稱 ； 雙重 ； 暈邊 ； 金氧半場效電晶體

並列摘要

In this thesis, a novel double-patterning technique has been successfully developed and applied to fabricate NMOSFETs with 100 nm gate length using I-line stepper. The method includes twice the lithography and subsequent etching process steps to form the gate patterns. Although more complicated, the approach is useful to lower the impact of diffraction effect on resolution limit. Therefore, this technique has better resolution capability and yields much better control over critical dimension variations that can be achieved by single-patterning. In addition to such capacity in patterning smaller gate length, double-patterning technique is also feasible for fabricating devices with asymmetric halo source/drain (S/D). In this work, we’ve also studied and analyzed the effects of asymmetrical halo implantation on the device characteristics, including hot-electron degradation and low-frequency noise performance.
We found that the halo implantation helps reduce the subthreshold leakage and improves the short channel effects (SCE), but it also causes severe reverse short channel effect (RSCE) and reduces the drive current. For reliability issue, the halo implantation would aggravate the hot-carrier degradation due to an increase in the strength of the lateral electric field under the gate edge in the devices. Using source-side halo devices, the hot carrier immunity is improved as compared to the drain-side halo sample, which is attributed to reduced peak electric field near the drain end.
Finally, we have also investigated the impacts of halo implantation devices on the low frequency noise characteristics. Halo implantation causes non-uniform threshold voltage distribution, resulting in the degradation of low frequency noise in short channel devices.

並列關鍵字

asymmetric ； double-patterning ； Halo ； MOSFET

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