針對可變動延遲設計時序變動之分析及最佳化

Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability

蔡長霖(Chamg-Lin Tsai)

指導教授 ： 吳凱強

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2016年)

摘要

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is pro-posed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing slack of 10% can be obtained without lengthening the clock period, and only 4% area overhead is introduced.

關鍵字

可變動延遲設計 ； 靜態時序分析 ； 時序變動 ； 邏輯匝置換 ； 粒子群體最佳化

並列摘要

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is pro-posed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing slack of 10% can be obtained without lengthening the clock period, and only 4% area overhead is introduced.

並列關鍵字

Variable-latency design ； Static timing analysis ； Timing variability ； Gate sizing ； Particle swarm optimization

參考文獻

[1] L. Benini et al., “Telescopic units: a new paradigm for performance optimization of VLSI designs,” IEEE TCAD, vol. 17, no. 3, pp. 220-232, March 1998.

[2] L. Benini et al., “Automatic synthesis of large telescopic units based on near-minimum timed supersetting,” IEEE Trans. on Computers, vol. 48, no. 8, pp. 769-779, Aug. 1999.

[3] Y.-S. Su et al., “An efficient mechanism for performance optimization of variable-latency designs,” in Proc. of DAC, pp. 976-981, June 2007.

[4] D. Baneres, J. Cortadella, and M. Kishinevsky, “Variable-latency design by function speculation,” in Proc. of DATE, pp. 1704-1709, April 2009.

[5] Y.-S. Su et al., “Performance optimization using variable-latency design style,” IEEE TVLSI, vol. 19, no. 10, pp. 1874-1883, Oct. 2011.