考慮製程變異與老化效應之類比電路可靠度自動化設計方法

Automated Robust Design Optimization of Analog Circuits Considering Process Variations and Aging Effects

陳彥龍(Yen-Lung Chen)

指導教授 ： 劉建男

國立中央大學/資訊電機學院/電機工程學系/博士(2014年)

摘要

隨著元件尺寸的遽縮，電路設計者須考量的非理想效應亦隨之增加，如電路寄生效應、製程變異、電路老化效應等等，這些效應對電路效能之影響甚為劇烈。若能在電路設計初期，即評估非理想效應對於電路效能之影響，則可降低重新設計的時間與成本。因此，本論文提出一套有效考慮非理想效應之類比電路自動化設計流程，可從電路規格產出到實際電路佈局，設計所有電晶體、電路元件參數。同時在設計階段，分別考量電路寄生效應、製程變異與電路老化效應對於電路效能之影響，有效避免設計的電路不符合電路規格之情況。

首先，本論文提出一套電路設計自動化流程，可在電路設計階段，將電路寄生效應加入考量，依據電路樣板，評估電路佈局前與佈局後的效能差異，並以此為依據，進行修正與最佳化，可避免電路效能在實際佈局後，出現不符合使用者規格之情況。

第二部分介紹本論文所提出的改良式製程變異之分析技術，可快速分析電路效能在製程變異影響下的變動程度及良率(yield)，而不需進行費時的模擬程序。結合此分析方式，所提出之最佳化流程，不僅可提升良率評估的速度及準確性，並能同時將電路面積與功耗視為最佳化之目標，如此，可確保設計之電路在擁有高良率的同時，亦保有小面積與低功耗之特性。

第三部分介紹本論文提出的階層式電路可靠度分析流程，可同時考量製程變異與電路老化之現象，結合此分析方法後，即可快速且準確地獲得製程變異與電路老化之資訊，如此，有效確保所設計之電路在一定使用時間之後，仍可符合電路規格。

由實驗結果可知，本論文所提出的電路自動化設計流程，確實可有效考慮電路非理想效應對於電路效能之影響，並且修正電路參數，以符合電路之規格，並提升設計的良率。此外，本論文提出之設計流程亦可達到較小的電路面積與功率消耗，並能依使用者之需求彈性調整目標。相信如此的方式，能幫助設計者面對深次微米製程的挑戰，並加速電路設計之流程。

關鍵字

類比設計自動化 ； 製程變異 ； 寄生效應 ； 元件老化 ； 良率 ； 軟性電子

並列摘要

With shrinking device size in deep submicron process, many non-ideal effects impact circuit performances critically. If those non-ideal effects can be considered in the early design stage, the re-design and re-spin cost can be avoided. Thus, a reliable design flow from specification to fabrication is presented, which consider parasitic effects, process variations, and aging effects.

Firstly, a layout-aware automated design flow is proposed in this dissertation to consider the layout-induced parasitic effects based on a flexible layout template. Therefore, the case that the performance fails to meet the specifications after layout can be avoided.

Secondly, a modified equation-based variance analysis method is proposed to calculate each performance variations without simulations. It can be used to improve the accuracy of yield prediction for each possible solution in equation-based optimization. This design flow enables simultaneously optimization with other design objectives like power or area cost to prevent unnecessary over-design.

Finally, a hierarchical reliability analysis and a reliable design flow is proposed to estimate the performance degradation considering process variations and aging effects simultaneously. With the fast and accurate prediction of degradation effects, the fresh yield and lifetime yield are considered simultaneously at the sizing stage.

As shown in the experimental results, the proposed method ensures the performance after layout due to accurate prediction the parasitic effects. Also, this design flow can further improve the fresh yield and lifetime yield, and the design overhead is reduced significantly with within a fast computation time.

並列關鍵字

Analog Design Automation ； Process Variation ； Parasitic Effect ； Aging Effect ； Yield ； Flexible Electronics

參考文獻

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