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  • 學位論文

利用三維串列對稱網格模擬P-N球接面之崩潰現象

Breakdown Simulation of a Spherical P-N Junction with a String of 3D Symmetrical Grids

指導教授 : 蔡曜聰
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摘要


本論文主要研究方向為開發串列對稱網格,探討其架構規則性,並加入離子撞擊游離模型於三維模擬器內,用以模擬半導體元件內部載子雪崩崩潰之物理現象。在理論基礎方面,我們運用波松方程式、電子流連續方程式與電洞流連續方程式,模擬三維半導體元件中載子漂移、產生與複合之特性。模擬架構方面,先研究串列網格之規則性,再藉由網格對稱性的原則,推導出模擬元件所需之各項物理參數。   最後我們應用此開發模擬模型,分析比較在不同擴散半徑與相異參雜濃度下其崩潰電壓的改變狀態,與其相對應關係為何,並與三維直角座標之撞擊游離模型進行比較,進而驗證本研究所開發之串列對稱網格模型不但具備模擬結果相同之準確性,更有效縮短崩潰模擬的時間為原本的四萬分之一,大幅提昇元件設計的便利性。

並列摘要


The paper aims to develop a string of 3D symmetrical grids to simulate the breakdown of a spherical P-N junction. Firstly, the regularity of 3D symmetrical grid is discussed. Secondly, with the purpose of finding the result of avalanche breakdown in P-N junction, the impact-ionization model is added into the 3D model. The Poisson equation and the equations of continuity for electron and hole are formulated into a subcircuit format, which are suitable for general circuit simulator in the equivalent circuit approach. The rule of embedding the symmetrical grids into the subcircuit format is analyzed to get the required parameters. Thirdly, the proposed model was applied to compare its breakdown voltage on different junction radius and different doping concentration to get the relationship on these parameters. Lastly, compared to the model in 3D rectangular coordinates, the 3D symmetrical grid is highly accurate and very fast for the breakdown simulation of a spherical PN junction.

參考文獻


[1] C. C. Huang. “Semiconductor Devices with 16nm Technology”, NARL Quarterly, 28, pp. 86-91, Oct. 2010.
[3] C. C. Chang, “Verification of 1D BJT Numerical Simulation and its Application to Mixed Level Device and Circuit Simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2001.
[5] C. C. Chang, C. H. Huang, J. F. Dai, S. J. Li, and Y. T. Tsai, “3-D Numerical Device Simulation Including Equivalent-Circuit Model”, IEDMS, 2002.
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[9] C. C. Chang, J. F. Dai, and Y. T. Tsai, “Verification of 1D BJT Numerical Simulation and its Application to Mixed-Level Device and Circuit Simulation”, Int. J. of Numerical Modelling: Electronic Networks. Devices and Fields, pp. 81-94, 2003.

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