應用時間借取與升壓加速機制之協作式電壓調變系統設計

Collaborative Voltage Scaling Scheme for Time-Borrowing & Local-Boosting Design

柳鍾凌(Chung-Ling Liou)

指導教授 ： 王進賢

國立中正大學/工學院/電機工程學系/碩士(2013年)

摘要

動態電壓調變(DVS)技術一直是低功率設計中最直接有效的方式之一，並且已廣泛應用在處理器為主的產品中，而可進一步隨晶片實際操作環境調整的適應性電壓調變(AVS)，能比傳統DVS獲得更多的功率節省，是目前將電壓控制在接近最低功率操作點的最佳方式。然而隨著製程演進，不斷增強的晶片間與晶片內變異造成傳統AVS架構中核心的效能監測電路設計受到準確度下降與成本增加的挑戰，因此本研究提出針對時間借取與升壓加速(TBLB)機制搭配的晶片內建效能監測器來改善傳統AVS架構中遇到的問題。
本研究採用同時具有直接與間接類型效能監測器的協作式電壓調變(CVS)架構，藉由特化效能監測器的設計，使其可同時提供量化的關鍵路徑延遲資訊、晶片整體製程邊界偏移資訊以及溫度區間資訊，如此一來系統將可隨晶片操作環境變化來動態修正各項CVS中的設計參數，包含關鍵路徑映射係數與目標警告率的最佳化，使電壓控制更接近不同情況的理想設定。
在本研究提出的效能監測器中，所有的偵測機制都採用環形震盪器搭配計數器架構，具有構造簡單、量測範圍可彈性調整並且較能抵抗晶片內變異誤差的特性。關鍵路徑延遲監測使用或及反閘(OAI)作為延遲細胞組成延遲線，配合製程邊界與溫度進行映射係數校正以提高準確度。製程邊界偵測使用P型電晶體主導延遲線、N型電晶體主導延遲線、雙層疊接反閘延遲線三種延遲線互相配合，可以在幾乎不受溫度影響的情況下判斷當前落在TT、SS、FF、SF、FS五個製程邊界的哪個位置。溫度偵測使用一般反相器延遲線，但藉由製程邊界的資訊進行換算補償，即可獲得滿足系統校正需求的準確度。
藉由IIR濾波器做為測試電路，模擬驗證TBLB搭配本次設計之效能監測器以及CVS控制流程，與傳統最差情況設計相比理想情況可最多獲得50%功率降低，並且與傳統錯誤率基礎電壓控制系統有更快速收斂達到最佳操作點的能力。

關鍵字

時間借取 ； 適應性電壓調變 ； 動態電壓調變 ； 效能監測器 ； 變異容忍

並列摘要

Dynamic Voltage Scaling(DVS) scheme is well used in high performance products such as Central Processing Unit in recent years, and has proved to be an efficient method to reduce power or energy consumption. Beyond the DVS, researchers have proposed an further aggressive scheme called Adaptive Voltage Scaling(AVS) which composed with on chip performance monitor and can utilize the remaining timing slack that was inside the voltage safety margin of traditional DVS.
Although AVS seems have trend to replace DVS in low power design, but there comes the problems when newly technology node shows more and more variation that affect circuit performance, which means that the real chip is fewer predictable through tradition simulation flow, and in the end reduce the accuracy of performance monitor or increase design cost. This is caused by greater inter-die and intra-die variation with process scale down and SOC complexity increased.
We proposed a new performance monitor that fit with the time-borrowing & local-boosting design under Collaborative Voltage Scaling(CVS) scheme, which is a AVS based scheme but have more flexibility in application. The monitor we proposed contain several different delay lines and act as ring oscillator, then record frequency information by counters. A special structure delay line response for modeling the critical path delay, and another set of delay lines for process corner detection without temperature issue, and the last delay line for temperature region detection. The above three kind of chip information helps voltage control system to choose delay mapping coefficient, and target warning rate with different situation.
We use an IIR filter as test vehicle to verify every design features and to identify progress of power saving ability in different situations.

並列關鍵字

time borrowing ； adaptive voltage scaling (AVS) ； dynamic voltage scaling (DVS) ； performance monitor ； variation tolerance

參考文獻

[2] B. H. Calhoun, and A. P. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering" IEEE

[3] K. Hirairi, Y. Okuma, H. Fuketa, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO," in IEEE ISSCC 2012 Dig. Feb. 2012, pp. 486-488

[4] M. Wirnshofer, L. Heiss, A. N. Kakade, N. P. Aryan, G. Georgakos, and D. Schmitt-Landsiedel, , "adaptive voltage scaling by in-situ delay monitoring for an image processing circuit," Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on , pp.205-208, 18-20 April 2012

[6] A. K. Uht, “Uniprocessor performance enhancement through adaptive clock frequency control,” IEEE Transactions on Computers, vol. 54, no. 2, pp. 132-140, February 2005.

[7] Junyoung Park, and J. A. Abraham, "A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems," Low Power Electronics and Design (ISLPED) 2011 International Symposium on , pp. 391-396, 1-3 Aug. 2011