TBLB和Dithered TBLB CMOS電路的可測性設計與分析

Testable Design and Analysis of TBLB and Dithered TBLB CMOS Circuit

潘昱夫(Yu-Fu Pan)

指導教授 ： 王進賢

國立中正大學/工學院/電機工程學系/碩士(2014年)

摘要

本論文改良了一項嶄新的低功耗技術TBLB[1]並稱之為Dithered TBLB，使其能自動地針對環境的變異以及操作的複雜度變異進行操作電壓的修正，達到即時追蹤最低功耗點的作用。其後將TBLB與Dithered TBLB加入量產化的快速測試機制，使該技術能跟實務界能夠更快接軌。在加入量產化快速測試機制時會使系統架構以及電路架構更加地複雜化，電晶體數也會提升。如何在加入量產化快速測試機制後依舊能維持原先技術的效能是本論文的一大課題，本論文也針對該課題進行TBLB電路架構本身的優化。本論文在28nm先進製程下針對TBLB[1]以及Dithered TBLB的電路架構的修改以進行量產化快速測試機制的運作後，透過一個小型的管線系統以及大型的管線系統以驗證快速驗證功能的操作。

關鍵字

可測性設計與分析

並列摘要

In this paper, we improved a new low-power technology TBLB[1], we named Dithered TBLB. The Dithered TBLB can automatically correct supply voltage for variability and complexity of operating environment, and achieve real-timing tracking the lowest power point. The mass production of rapid testing mechanism makes the system architecture and circuit architecture complex, the number of transistors will also enhance. How to maintain the effectiveness of original technology after adding a rapid testing mechanism is an important issue. In this paper, we modify TBLB[1] and Dithered TBLB circuit architecture for rapid testing mechanism in 28nm process. After that, we check the function of the rapid testing mechanism though a small pipeline system.

並列關鍵字

TBLB

參考文獻

[3] 國立中正大學電機工程研究所，許耿彰，"以TBLB及Dithered TBLB技術設計低功耗MSP430之研究"

[10] Bull, D.; Das, S.; Shivshankar, K.; Dasika, G.; Flautner, K.; Blaauw, D., "A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.284,285, 7-11 Feb. 2010

[11] 國立中正大學電機工程研究所，柳鐘凌，"應用時間借取與生壓加速機制之協作式電壓調變系統設計"

參考文獻

[1] Jinn-Shyan Wang; Keng-Jui Chang; Tay-Jyi Lin; Prasojo, R.W.; Chingwei Yeh, "A 0.36V, 33.3 µ W 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS," VLSI Circuits (VLSIC), 2013 Symposium on , vol., no., pp.C254,C255, 12-14 June 2013