以TBLB與Dithered TBLB技術設計低功耗MSP430之研究

Design of Low Power MSP430 based on TBLB and Dithered TBLB CMOS Technique

許耿彰(Keng-Chang Hsu)

指導教授 ： 王進賢

國立中正大學/工學院/電機工程學系/碩士(2014年)

摘要

歷年來有關AVS的作品大部分都著墨在偵測電路與時序修復行為，並沒有針對設計流程進行描述，設計者必須揣摩實作過程，常常細節部分一不小心就會造成整體功率不降反升，更嚴重會導致整個電路時序錯亂。有鑑於此，本論文將會以目前新穎的AVS技術TBLB規劃一套設計流程，講求可重製性(Reproducible)，讓設計者不管以什麼電路為實作目標，照著設計流程實作就可以實現TBLB的行為並且功耗表現比一般針對worst case設計的方法還要來的好。本論文將以16-bit乘法器與目前在無線感測網路應用上相當熱門的MSP430微控制器作為實作的載具，透過分析乘法器與MSP430的架構再搭配提出之TBLB設計流程，快速實現TBLB的行為與效果。

關鍵字

微處理器 ； Dithered TBLB ； TBLB ； 低功耗設計流程 ； 低功耗 ； MSP430 ； 管線設計

並列摘要

Over the years, most of the works about the AVS techniques are force on timing-error detection circuit and timing recovery. No works indicate the design flow of the technique. The designer must try to figure out implementation details. However, if the details are not clear it will cause the circuit power consumption rise; more serious would make the whole circuit timing fail. Therefore, we plan a design flow of TBLB-style design and emphasize the reproducibility. Designers implemented according to our design flow can achieve TBLB behavior and the power consumption better than the worst case design flow. We use 16-bit multiplier and MSP430 microcontroller as test vehicles and follow TBLB design flow. Quickly realize TBLB on both circuits.

並列關鍵字

microprocessor ； Dithered TBLB ； TBLB ； low power design flow ； low power ； MSP430 ； pipeline design

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