多輸入輸出正交分頻多工系統下預編碼子系統之硬體實現

Hardware Implementation of the Precoding Sub-System in MIMO-OFDM Systems

林洋正(Yang-Cheng Lin)

指導教授 ： 劉宗憲

國立中正大學/工學院/通訊工程學系/碩士(2014年)

摘要

近年來由於無線通訊的蓬勃發展，使用多輸入輸出 (Multiple Input Multiple Output , MIMO) 與正交分頻多工 (Orthogonal Frequency Division Multiplexing , OFDM) 結合的系統已經成為無線通訊發展的主流趨勢。 MIMO 衍生出許多相關技術，有空間多工 (Spatial Division Multiplexing , SDM)，空時區塊碼 (Space Time Block Codes , STBC) 和預編碼 (precoding)，其中預編碼子系統是本論文所探討的重點，預編碼為 MIMO-OFDM 系統提升訊號接收的品質 (quality) 與資料可靠性 (reliability)。
本論文中主要利用雙對角線矩陣 (bidiagonal matrix)和奇異值分解 (Singular Value Decomposition , SVD) 演算法，並且以 CORDIC (COordinate Rotation DIgital Computer) 模組來實現預編碼硬體架構且需符合 IEEE 802.11n 標準。本論文預編碼硬體架構設計 4×2 , 3×2 和 2×2 的通道矩陣，利用回傳角度值的方式，將角度值由接收端回傳至傳送端以重建預編碼矩陣，達到減少約 75% 回傳的資料量。在硬體實現上，使用 Xilinx ISE 12.2 來完成 Verilog HDL 撰寫並使用 FPGA 模擬板來合成電路，以及內建的驗證軟體來觀察電路函數的正確性。最後以 Synopsys Design Compiler 並採用 TSMC 90 nm CMOS 製程來進行 ASIC 電路合成，其 gate count 分別為 122.8 k , 89.4 k , 56.5 k 與操作頻率為 100.7 MHz，而 SVD throughput rate(matrix/sec) 分別可達到 16.8 M , 20.1 M , 25.2 M。

關鍵字

奇異值分解 ； 雙對角線矩陣 ； 預編碼 ； 正交分頻多工 ； 多輸入輸出

並列摘要

As the wireless communication prevails, various multiple input multiple output with orthogonal frequency division multiplexing (MIMO-OFDM) techniques have attracted much attention in recent years. Among the three major MIMO techniques, including spatial division multiplexing (SDM), space-time block code (STBC), and precoding, precoding is the emphasis of this thesis. Precoding for the MIMO system provides better transmission quality and reliable data transmission.
The antenna configuration includes two transmit antennas and the number of receive antennas may be 2, 3, or 4. The studied precoding system requires that the angles to represent the right singular vectors of the channel matrix are to be feedback to the transmitter side. Such feedback can reduce the number of bits to be feedback to the transmitter side by about 75%. Algorithm and hardware architecture for the precoding used in the IEEE 802.11n are studied. The complete algorithm includes bi-diagonalization
and singular value decomposition of the channel matrix. The architecture relies on the CORDIC module. The designed architecture is described by Verilog HDL, and verified and synthesized in the Xillinx ISE 12.2 FPGA environment. Finally, synthesized by Synopsys Design Compiler with TSMC 90 nm CMOS technology, the designed architectures for the 4-by-2, 3-by-2, and 2-by-2 channel matrices require 122.8 k, 89.4 k, and 56.5 k gates and provide SVD throughput rate 16.8 M, 20.1 M, 25.2 M matrices/sec, respectively, while operating at frequency 100.7 MHz.

並列關鍵字

coordinate rotation digital computer (CORDIC) ； Givens rotation ； singular value decomposition (SVD) ； precoding ； bidiagonal matrix ； orthogonal frequency division multi- plexing (OFDM) ； multi-input multi-output (MIMO)

參考文獻

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