完全符合IEEE 802.11n/ac 無線區域網路下壓縮波束成形權重反饋預編碼的計算演算法與硬體實現

Exact Hardware Implementation for the Calculation Compressed Beamforming Weights Feedback in the IEEE 802.11n/ac WLAN

陳育傑(YU-JIE CHEN)

指導教授 ： 劉宗憲

國立中正大學/工學院/通訊工程學系/碩士(2016年)

摘要

摘要
在IEEE 802.11n/ac WLAN 規格下的OFDM-MIMO 系統中, 接收端為了使
用最少的資料量回傳傳送端所需的訊息以重建預編碼矩陣, 常使用壓縮波束成形權
重反饋技術(Compressed Beamforming Weights Feedback, CBWF) 。將此技術應用
在系統中, 接收端會估測每個子載波上的通道矩陣, 預編碼子系統將會使用QR
分解和奇異質分解(Singular Value Decomposition, SVD) 將通道矩陣拆解, 並且
以CORDIC(Coordinate Rotation Digital Computer) 模組來實現硬體架構, 處理量
化後所得到的角度回傳給傳送端以重建預編碼矩陣。本論文硬體架構設計適用於傳
送端架設四根天線, 接收端架設兩根天線, 即適用於2×4的通道矩陣, 並引用本
論文改善過的TACR-TSA 硬體架構[29] 、SVD 演算法硬體架構[30]和Quantize 硬體
架構[31] , 其中TACR-TSA 架構在演算過程中使用到兩次以符合IEEE 802.11n/ac
的規格為本論文之重點, 在硬體上使用Xilinx 14.7進行Verilog HDL 撰寫並使用
FPGA模擬板來合成電路以及驗證。最後使用Synopsys Design Compiler並使用TSMC
90nm CMOS 製程來進行ASIC 電路合成, 其gate count 為114.4K 且操作頻率為
100.5MHz 。

關鍵字

壓縮波束成形權重反饋 ； 奇異值分解 ； 預編碼 ； 正交分頻多工 ； 多輸入多輸出

並列摘要

The IEEE 802.11n / ac WLAN specification is an example of the OFDM-MIMO system
to realize compressed beamforming weights feedback (CBWF) technology. In this system,
the feedback information is minimal and the feedback of channel information can
be finished in a very short time. It is important that the channel at the time the precoded
data are transmitted is approximately the same as the time the channel is estimated at
the receiver. The precoding sub-system at the receiver to compute the feedback information
is important to the success of this precoding procedure. To compute the CBWF
information, at the first step, the precoding sub-system needs to perform singular value
decomposition (SVD) to obtain the right singular vectors of the channel matrices at
all sub-carriers. At the second step, precoding sub-system needs to perform QR decomposition
(QRD) to compute the angles representing the right singular vectors. The
quantized angles are then fed back to the transmitter side, so that the transmitter can
reconstruct the precoding matrices from these quantized angles. The exemplary antenna
configuration of 4 transmit and 2 receive antennas are considered in this thesis.
The well-known three angle complex rotation triangular systolic array (TACR- TSA) is
used in our architecture for the SVD and QRD computation. Our designed architecture
is described by Verilog HDL, verified and synthesized in the Xillinx ISE 14.7 FPGA
environment. Also, the VLSI implementation results under the TSMC 90 ns CMOS
technology reveal that our architecture requires 114.5K gates while operating at frequency
100.5 MHz.

並列關鍵字

singular value decomposition ； Compressed Beamform- ing Weights Feedback ； precoding ； orthogonal frequency division multiplexing ； multi-input multi-output ； coordinate rotation digital computer

參考文獻

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Hall, 2005.

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