背景式增益誤差校正十位元每秒五千萬次取樣率管線式類比數位轉換器

A 10-bit 50MS/s Pipelined ADC With Background Gain Error Calibration

賴炳文(Bing-Wen Lai)

指導教授 ： 蔡宗亨

國立中正大學/工學院/電機工程學系/碩士(2014年)

摘要

本論文提出一個十位元、取樣率為每五千萬次且具有增益誤差背景式校正管線式類比數位轉換器，此類比數位轉換器在0.18-m CMOS製程下實現。整個電路中主要的重點就是解決增益誤差的問題，雖然之前就有不少論文有提出有關增益誤差的校正方法，不過比較早的增益誤差校正通常都需要三個相位，這會影響到運作速率，而此篇論文只需要兩個相位就可以達到增益誤差的校正，而且也不需要額外的電路。此論文的管線式類比數位轉換器的供應電壓為1.8V，10位元取樣頻率為50MS/s、輸入頻率為24.56MHz，佈局後的模擬結果， SNDR為57.22dB、ENOB為9.21bit，功率消耗為19.2mW。

關鍵字

增益誤差 ； 管線式類比數位轉換器 ； 背景式誤差校正

並列摘要

This work presents a 10bit 50MS/s pipelined analog-to-digital (ADC) with background gain error calibration. This pipelined ADC is implemented in a 0.18-um CMOS process technology. This circuit is to calibration gain error. Although there are many papers presented before the calibration of the gain error, but earlier gain error calibration usually requires three phases. This will affect the sampling rate. This paper requires only two phases, we can achieve gain error calibration circuit. And does not require additional circuit. An 10bit 50MS/s prototype pipelined ADC has been fabricated in 0.18-um CMOS. The overall power dissipation is 19.2mW from a 1.8V supply. With a 24.56MHz input frequency. This pipelined ADC SNDR is 57.22dB, and ENOB 9.21bit.

並列關鍵字

Background calibration ； Gain error ； Pipelined ADC

參考文獻

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