近年來由於無線通訊的蓬勃發展, 使用多輸出多輸入(MIMO) 系統已經成為 無線通訊發展的主流趨勢, 此外, MIMO衍伸出許多相關技術, 其中預編碼(precoding) 技術是本論文所探討的重點。一般來說, 在實際的系統中, 利用常見的挑 選法則(selection criterion) 從編碼簿(codebook) 中可以挑選出最適合的碼字(codeword) 當作預編碼矩陣(precoding matrix) , 預編碼為MIMO-OFDM 系統提升訊號 品質(quality) 與資料可靠性(reliability) , 本論文所使用的編碼簿為LTE 下行鏈路 的編碼簿。 本論文中主要利用MMSE Trace Criterion 有矩陣的對稱性以及利用LDLH分 解, 還有利用backward substitution來避免反矩陣運算, 進而減少selection criterion 的運算複雜度, 來實現預編碼簿(codebook) 中挑出碼字(codeword) 的硬體架構且 須符合3GPP LTE標準。在硬體實現上, 使用Xinlinx ISE 12.2來完成Verilog HDL 撰寫並使用FPGA 模擬板來合成電路, 以及內建的驗證軟體來觀察電路函數的正確 性。最後以Synopsys Design Compiler並採用TSMC90nm CMOS製程來進行ASIC 電路合成, 其gate count 為156.22K 與操作頻率為170MHz , 而MMSE Trace Criterion throughput rate(matrix/sec) 為14.17M 。
As the wireless communications prevails, various MIMO techniques attract much attention in recent years. Among the various MIMO techniques, the limited feedback precoding is the focus of this thesis. The precoding matrix at the transmitter side is selected from a finite-sized codebook. The LTE-Advanced downlink codebook is considered in this thesis. In this thesis, we use the MMSE Trace Criterion and LDL^H matrix decomposition. Then, we use the backward substitution to avoid matrix inversion operations. Therefore, we can reduce the computational complexity of the proposed hardware architecture for selecting a single codeword from 3GPP LTE codebook. On the hand, the designed hardware architecture was synthesized and verified in the Xilinx ISE 12.2 environment and also synthesized by Design Compiler. The designed architecture requires is 156.22K gates and work with frequency 170 MHz under the TSMC 90 nm CMOS technology. The designed architecture computes such precoding matrices with throughput rate 14.17M matrices/second.