用於超低電壓訊號處理之可變延遲查表與概略式分散算術

Variable-Latency Table Lookup and Approximate Distributed Arithmetic for ULV Signal Processing

張政鈞(Cheng-Chun Chang)

指導教授 ： 林泰吉

國立中正大學/工學院/資訊工程學系/碩士(2015年)

摘要

基於記憶體的計算方法主要消耗的能量為查表，已知自適性電壓已成功用在邏輯電路上，因此使用自適性電壓調降記憶體的電壓來達到省能量的效果並保持其效能，本論文在研究使用自適性電壓時，電壓過度調降（VOS）發生造成讀取記憶體時的異常，需要額外的幾個週期在讀取一次，本論文提出零計數（zero count; ZC）來比較各個錯誤偵測機制，還提出概略式算術（approximate distribute arithmetic; ADA）並結合可變延遲查表（variable-latency LUT）與時序錯誤檢測器，此錯誤容忍機制可以大大降低因超低電壓下所造成的系統故障問題並保持系統的品質，最後我們實驗分析出SNR與能量的折衷，可以知道在0.60V下ZC的SNR值還能為48.21。

關鍵字

零計數 ； 可變延遲查表 ； 自適性電壓調整 ； 概略式分散算術

並列摘要

Memory-based computing is a system that the computational functions are permed by lookup table (LUT) that mainly energy is spent on the memory. Adaptive voltage scaling (AVS) already could be used to logic circuit, and we using adaptive voltage scaling to scale the voltage of memory for saving energy that keeps quality well. When voltage over scaling (VOS) is happed that lead to the read operations abnormally, the read operations need extra some cycle. We proposed the zero count to detect the faults. We also proposed the approximate distribute arithmetic (approximate distribute arithmetic; ADA) that combined the variable-latency table and timing fault detector. The fault tolerant technique could reduce the error of system at low voltage and keeps the quality well. Finally, we evaluate the tradeoff between SNR and energy. At the 0.60V, ZC could keep SNR value is 48.21.

並列關鍵字

Zero count ； Variable-latency table lookup ； Adaptive voltage scaling ； Approximate distribute arithmetic

參考文獻

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