應用於光接收機中寬頻放大器之頻寬延伸技術

Bandwidth extension techniques for wideband amplifiers in optical receivers

詹承達(CHAN CHENG-TA)

指導教授 ： 陳自強

國立中正大學/工學院/電機工程學系/博士(2016年)

摘要

這篇論文中我們分析與設計了無電感式頻寬延伸技術。我們分析RGC電路之轉換方程式並推導出結合增益、頻寬與製程參數 之評估公式而有助於RGC電路之參數設計。隨著設計取向的不同，為了增加高增益RGC電路之頻寬我們提出三級內插式主動回授架構，分析其回授參數產生增益突峰(gain peaking)之效果增加整體系統之頻寬。另一方面為了補足寬頻寬RGC之增益我們分析了N階主動式回授(N-order active feedback)之架構，求得放大器細胞(amplifier cell)之增益-頻寬與整體架構之增益-頻寬關係與曲線特性。為了進一步增加頻寬並補償寬頻RGC之增益，我們提出了多層主動式回授架構(multi-level active feedback)。由轉換方程式分析與利用不同製程模擬顯示出此架構有不錯之增益並能大幅延伸頻寬。為了驗證我們提出之架構，我們分別設計了10Gbps 轉阻放大器、10Gbps轉阻限幅放大器、40Gbps 限幅放大器以及40Gbps 轉阻限幅放大器。其中10Gbps 轉阻放大器利用TSMC 180奈米製程製作並量得了180mVpp之眼狀圖、65dBΩ之差動轉阻增益與7.2GHz之頻寬。10Gbps轉阻限幅放大器以內插式主動回授架構來實現增益突峰之效果，藉此增加整體系統之頻寬。同樣利用TSMC 180奈米製程製作而量得了4.4kΩ之差動轉阻增益與220mVpp之眼狀圖。由於使用90奈米製程來實現40Gbps放大器其 之增加無法補償資料速率(data rate)之增加而使得設計符合規格之架構更為困難，因此我們提出了高增益多階層回授架構加上串接電感來達成目標並驗證架構。在此架構下，40Gbps 限幅放大器可模擬出400mVpp之眼狀圖、40dB之差動增益與36GHz之頻寬。最後40Gbps 轉阻限幅放大器可模擬出600mVpp之眼狀圖、85dBΩ之差動轉阻增益與35GHz之頻寬。由上述四顆晶片之實現模擬與量測可以了解到本論文所提出之無電感式頻寬延伸架構可有效的提升頻寬。

關鍵字

多層主動式回授 ； 限幅放大器 ； 轉阻放大器 ； 無電感式頻寬延伸 ； 內插式主動回授 ； 增益突峰

並列摘要

In this dissertation, an inductor-less bandwidth extension technology was designed and analyzed. The conversion equation of a regulated cascade (RGC) circuit was analyzed to determine an evaluation formula for combined gain, bandwidth and process parameters (Ft). This formula facilitates the parameter design of the RGC circuit. To enhance the bandwidth of high-gain RGC circuits, the three-stage interleaved active feedback was proposed in the present study. The gain peaking effect generated by the feedback parameters and its influence on the bandwidth of the overall system were analyzed. Alternatively, the gain-bandwidth relationships between amplifier cell in Nth-order active feedback and overall system of Nth-order active feedback architecture was also analyzed to compensate for the gain of wide-bandwidth RGC. To further improve the bandwith, the multi-level active feedback is proposed. The conversion equation and process simulation results indicate that the proposed architecture achieved favorable gains and significantly expanded bandwidths. To verify the proposed architecture, four different amplifiers were designed, namely, a 10Gbps trans-impedence amplifier, 10Gbps trans-impedence limiting amplifier, 40Gbps limiting amplifier, and 40Gbps trans-impedence limiting amplifier. The 10Gbps trans-impedence amplifier was produced using the TSMC CMOS 180nm process, achieving an eye diagram of 180mVpp, differential transimpedence gain of 65dBΩ, and bandwidth of 7.2GHz. The three-stage interleaved active feedback architecture of the 10Gbps trans-impedence limiting amplifier was adopted to elevate gain peaking and improve the overall bandwidth of the system. It was also produced using the TSMC CMOS 180nm process, achieving a differential trans-impedence gain of 4.4kΩ and an eye diagram of 220mVpp. Because the increase in Ft when using the 90nm process to produce the 40Gbps amplifiers was unable to compensate for the increase in data rate, making it difficult for the design to meet specification, a high-gain multi-level active feedback architecture coupled with series inductors was developed in the present study to reach the predetermined goal and verify the architecture. Using this architecture, the 40Gbps limiting amplifier simulations achieved an eye diagram of 400mVpp, differential gain of 40dB, and bandwidth of 36GHz. Finally, the 40Gbps trans-impedence limiting amplifier simulations achieved an eye diagram of 600mVpp, differential trans-impedence gain of , and bandwidth of 35GHz. The simulations and measurement results of the four ICs proposed in the present study confirm that the proposed inductor-less bandwidth extension architecture can effectively improve bandwidth.

並列關鍵字

interleaved active feedback ； multi-level active feedback ； limiting amplifier ； trans-impedance amplifier ； inductor-less bandwidth extension ； gain peaking

參考文獻

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