晶片厚度、膠材熱膨脹係數及銅凸塊位置對銅柱狀凸塊構裝 在熱壓接合及膠材硬化製程條件下之彈性應變能密度效應

Effects of chip thickness, thermal expansion coefficient of underfill material and location of Cu pillar bump on elastic strain energy density in a package under the conditions of thermal compression bonding and underfill curing processes

張曜安(Zhang Yao-An)

指導教授 ： 盧威華

國立屏東科技大學/工學院/材料工程研究所/碩士(2019年)

https://doi.org/10.6346/NPUST201900140

摘要

本文將探討以化學鍍錫的方式在晶片銅凸塊以及基板銅墊上鍍上錫層，並透過熱壓接合的方式將晶片組裝，銅凸塊構裝過三種可靠度試驗，並利用 ANSYS 軟體進行結構應力模擬，分析不同晶片厚度及改變膠材熱膨脹係數的銅柱狀凸塊在熱壓接合製程及膠材硬化製程下的彈性應變能密度分佈。另外，本研究將銅柱狀構裝體的晶片四個角落增加一顆無功能的銅柱狀凸塊，分析晶片上銅柱狀凸塊在熱壓接合及膠材硬化製程下的彈性應變能密度變化，並與未加入無功能的銅柱狀凸塊構裝進行彈性應變能密度模擬結果比較。

經模擬結果得知，在熱壓接合及膠材硬化製程後，von Mises stress 、von Mises elastic strain 與 Elastic strain energy density 值將會隨著晶片變薄而降低，翹曲值則會隨著晶片厚度變薄而升高。當在晶片角落增加一顆無功能之銅柱 狀凸塊，可使得應力較大位置改變於角落具無功能之銅柱狀凸塊而降低原始 銅柱狀凸塊的彈性應變能密度。

關鍵字

無電鍍錫 ； 銅柱狀凸塊 ； 應力模擬 ； 彈性應變能密度

並列摘要

In this study, tin were deposited on copper pillar bump and substrate copper pad by electroless plating method. By way of thermal compression bonding process, the chip with copper pillar bump was assembled on substrate. After the molding process, the package were tested for reliability evaluation. The package passed the temperature cycling, high temperature storage and temperature/humidity tests. Using Solidworks and ANSYS softwares, this study constructed a 3-D model to numerically investigate structural stress in a package under the conditions of reflow and underfill curing processes. This study also investigated the effect of the die thickness and coefficient of thermal expansion of underfill material on elastic strain energy density of a package.

In addition, the study will be held in four different corners of the chip added a non-functional copper pillar bump to compare not added with non-functional copper pillar bumps stress distribution of a package under the conditions of the thermal compression bonding and underfill curing processes.

The numerical results showed the von Mises stress, von Mises strain and elastic strain energy density decreased with decreasing the chip thickness and coefficient of thermal expansion of underfill material. When the chip corner added a non-functional copper pillar bump, stress can make a larger change in the position of having no function of the corner pillar bumps and reduced the stress and elastic strain energy density of the original copper pillar bumps.

並列關鍵字

Electroless plating tin ； Copper pillar bump ； Structural stress simulation ； Elastic strain energy density

參考文獻

1.DIGITMES企劃，2013，3D IC晶圓不同接合技術的技術難度與發展，科技網。

2.李洵穎，2011，銅柱凸塊，科技網。

3.Lau, J. H., Wong, C. P., Prince, J. L., and Nakayama, W.,1998, Electronic packaging: design, materials, process, and reliability.

4.Lofrano, M., Cherman, V., Gonzalez, M., and Beyne, E.,2018,“Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly,”Microelectronics Reliability, Vol. 87, pp. 97-105.

5.Chen, W. T., and Nelson, C. W.,1979,“Thermal stress in bonded joints,” IBM Journal of Research and Development, Vol. 23, No. 2, pp. 179-188.