高效能嵌入式視訊編碼位元率控制系統之研究

H.264是現今最常採用的商業視訊編碼標準，尤其是應用在視訊電話和視訊監控系統，然而早期視訊設備因硬體限制和價格考量，大多採用30萬畫素低解析度(640480)的視訊，因此當影像放大後常常導致品質不佳且模糊，以至於無法進行影像識別。為了克服此問題，本論文提出高效能視訊編碼位元率控制系統，並進一步嵌入至ADSP-BF548的數位訊號處理(digital signal processing: DSP)開發板中，來完成高解析度之H.264視訊編碼與傳輸的DSP實現。　　H.264視訊標準在測試平台(JM11.0)進行位元率控制時[5]，須先利用線性迴歸分析(linear regress analysis)來預測待編巨方塊(macroblock: MB)的平均絕對値差(mean absolute distortion: MAD)，再運用二次方位元量化模型(rate-quantization model: R-Q model)來達到各層的位元率控制(包括frame layer和MB layer)，並進行位元配置(bits allocate)和決定量化參數(quantization parameter: QP)，最後執行最佳位元失真(rate distortion optimization: RDO)完成編碼。但因H.264所採用R-Q的模型較簡單，常導致MAD預測的準確度不高，以致於視訊品質仍無法滿足要求。為了改善上述的問題，本論文利用自然視訊具有高時空相關性(spatio-temporal correlation)的本質，結合快速畫框內模式預測(intra-mode prediction)與位元率控制器，建構出一個高效能H.264位元率控制系統。由實驗結果可以發現在不同頻寬的傳輸通道下，本論文所提出的位元率控制演算法比JM 11.0更能達到穩定的視訊傳輸效能，並且提供較好的視訊品質，特別是在畫面變動率較高或者是場景變換的情形。　　此外，為了有效完成所提出H.264視訊位元率控制器在DSP硬體的實現，首先必須完成DSP內部記憶體最佳化配置，我們將高效能位元控制緩衝器配置在外部記憶體L3(DDR SDRAM)中，來提高解析度至19201080全高畫質(full high definition: FHD)視訊編碼，並將運動估測(motion estimation: ME)模組所需之參考畫面直接配置到內部記憶體L2(SRAM)中，進一步提升ME模組的執行效率。其次，我們利用Blackfin系列專用指令對程式碼進行撰寫與優化[11]，使程式能夠更流暢的運作於ADSP-BF548開發板，提高H.264整體編碼效率。最後，我們將所提的高效能H.264視訊編碼位元率控制系統，成功嵌入在ADSP-BF548開發板上，並完成實驗模擬與測試。　　經由不同解析度影像序列進行DSP硬體實驗結果顯示，本論文所提高效能H.264嵌入式位元率控制系統的視訊品質(PSNRY)比JM 11.0平均改善約0.59 dB，而且可以大幅改善JM11.0所造成的跳畫框情形。此外，經由最佳的記憶體配置，整體編碼的時間改善率(time improving ratio: TIR)平均約為44.07%。從實驗結果的驗證，論文所提方法確實能大幅提升H.264位元率控制效能，提供更穩定的視訊品質，適合直接應用在現今的視訊監控產品上。

關鍵字

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並列摘要

Nowadays, H.264 video standard is widely used in many commercial applications, especially used for videophone and surveillance systems. However, most of early surveillance equipment adopts low-resolution (640×480 pixels) video standard due to the consideration of hardware and cost. This leads to an obstacle for image recognition since the quality of enlarged image is poor and blurring. In order to overcome this problem, a highly efficient video rate control system is embedded on ADSP-BF548 digital signal processor (DSP). Finally, we achieve a H.264 baseline encoder for full high definition (FHD) video transmission. 　　When performing H.264 rate control (JM11.0) [16], a linear regression analysis is firstly used to predict mean absolute distortion (MAD) of macroblock (MB). Then, a quadratic rate-quantization (R-Q) model is adopted to reach rate control of each layer (including frame layer and MB layer). Finally, a proper quantization parameter (QP) is determined according to the number of allocated bits and R-Q model to achieve video rate control. However, traditional rate control schemes cannot meet the requirement of FHD video quality due to a simple R-Q model. To meet FHD video quality, an improved rate control scheme for low delay H.264 video coding is proposed in this thesis. A fast and best selection of initial QP is firstly proposed in the group of pictures (GOP) layer rate control. Then, an improved MAD prediction model and overhead bits prediction method is adopted in the MB layer rate control. 　　In order to achieve a FHD video low-delay requirement of embedded H.264 encoder based on ADSP-BF548, we use a highly efficient memory assignment technique to modify the allocated internal memory and optimize the source codes, separately. Firstly, the we analysis the complexity of encoding modules for H.264, and then we re-allocate the reference frame from L3 DDR-RAM to L2 SRAM to increase the speed of execution of ME module and re-allocate the function of consuming module from L3 DDR-RAM to L1 SRAM. Secondly, we make use of direct memory access (DMA) and the default function of ADSP-BF548 to carry out program steps. Finally, we completed the highly efficient embedded rate control for video encoding system based on ADSP-BF548 successfully. 　　Experimental results show that our proposed rate control system for FHD video can achieve an average PSNRY gain of about 0.59 dB when compared with JM11.0. In addition, the proposed scheme improves the number of frame skipped and reduces the quality deviations of the initial frames by choosing the best initial QP. Furthermore, we can achieve an average time improving ratio (TIR) about 44.07% when compared with the directly embedded H.264 encoder on ADSP-BF548. It is obvious that the proposed embedded H.264 video rate control system can be directly applied to consumer high-resolution video applications.

並列關鍵字

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參考文獻

[1]H.264/MPEG-4 Part 10 White Paper, http://www.vcodex.com/h264.html

[13]T. Chang and Y. Q. Zhang, “A new rate control scheme using a new rate-distortion model,” IEEE Trans. Circuit Syst. Video Technol., pp. 246-250, Feb. 1997

[14]A. Armstrong, S. Beesley and C. Grecos, “Selection of Initial Quantisation Parameter For Rate Control H.264 video coding,” Research in Microelectronics and Electronics, pp. 249-252, June 2006

[15]C. C. Wang and C. W. Tung.”Rate Control for Low Delay Video Communication of H.264 Standard, Recent Advances on Video Coding,” InTech, DOI: 10.5772/16792.

[16]C. W. Yu, C. C. Wang and J. Y. Kao, “An Improved Rate Control for Video Communication of H.264 Standard”, IEEE International Conference on Image Processing, pp. 1345-1349, Oct. 2006.

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高效能嵌入式視訊編碼位元率控制系統之研究

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