應用於DSP之高效率記憶體配置來實現H.264視訊編碼器

隨著行動通訊技術的迅速發展，各式各樣的行動多媒體服務也因應而生，像是行動視訊(mobile video)、網路多媒體串流(multimedia streaming)和行動電視(mobile TV)等等相關應用。而H.264是由聯合視訊小組(joint video team: JVT)制定的國際視訊編碼標準，和先前的視訊標準相比，除了影像品質和壓縮效能皆有相當大的改善外，H.264也能提供良好的網路親和力，以方便於在各種網路環境下傳輸位元流，因此更適合於行動通訊的應用。現今大多視訊產品採用H.264標準來取代MPEG-2，H.264已成為主流的視訊產品。有鑒於行動裝置上因為電池用量有限，所以多半都會整合一顆具有高效能且低功耗的數位訊號處理器(digital signal processor: DSP)晶片，因此本論文進一步將H.264系統嵌入至具有DSP晶片的ADSP-BF548開發模擬板來進行模擬與測試。然而，H.264為了能比以往視訊的標準有更高的壓縮效能，必須付出龐大的運算量，而導致對於運算速度及記憶體容量有限的行動裝置，無法達成即時(real-time)的視訊應用。因此，如果H.264編碼器在未經過系統規劃下，直接嵌入至硬體設備上，其編碼速度會變得相當的緩慢。為了能在嵌入式系統中提升H.264的編碼效率，本論文首先對於H.264各個模組，包括畫框內預測(intra prediction)、畫框間預測(inter prediction)、整數餘弦轉換(integer cosine transform: ICT)、量化(quantization: Q)、熵編碼(entropy coding)、去方塊濾波器(deblocking filter: DF)等模組進行運算複雜度的探討，再以ADSP-BF548開發H.264編碼器的設計，進一步考量記憶體的配置，並提出一高效率記憶體配置(highly efficient memory assignment: HEMA)演算法來實現嵌入式H.264系統。HEMA主要是依據H.264各個模組的運算複雜度之比重，並配合多階層記憶體架構的特性，將高運算量的模組從運算速度較慢的外部記憶體(external memory)，有效的重新配置在運算速度較快的內部記憶體(internal memory)來改善H.264的編碼效率。除了記憶體配置之外，為了能降低DSP對於H.264的運算負擔，本論文也利用快速畫框間模式決策演算法(fast inter mode decision algorithm: FIMDA)[23]，來大幅降低H.264龐大運算量的問題。經由不同的影像序列及量化參數(quantization parameter: QP)來進行測試與模擬，從實驗結果顯示，本論文所提HEMA演算法比直接將H.264編碼器嵌入於ADSP-BF548開發板的編碼時間改善率(time improving ratio: TIR)平均約為56%，若換算成加速率平均約為2.29倍。當將HEMA結合FIMDA時，TIR平均約可提升到84.7%，加速倍率平均約可達6.56倍左右。經實驗結果的驗證後，論文所提HEMA確實能大幅提升H.264的編碼效能，適合直接應用在現今的行動視訊電子產品上。

關鍵字

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並列摘要

With the rapid development of mobile multimedia technology, the applications of different mobile multimedia services are widely used in consumer electronics such as mobile video, multimedia streaming and mobile TV. To achieve these applications, the H.264 is a main video standard due to the higher compression performance than previous video standard. In addition, H.264 has a network-friendly video representation such that it is fitted for the mobile multimedia applications. To achieve high quality video under high compression rate, H.264 develops some new encoding modules including intra mode prediction, inter mode prediction, multiple reference frame prediction, integer cosine transform (ICT), entropy coding and deblocking filter. Since H.264 uses 7 variable block sizes (modes) ranging from 16×16 to 4×4 in inter mode prediction module, the motion estimation (ME) with 7 modes needs very high computational complexity. In order to achieve the fast requirement of embedded H.264 encoder based on ADSP-BF548, we propose a highly efficient memory assignment (HEMA) technique to modify the allocated internal memory and optimize the source codes, separately. Firstly, the HEMA analysis the complexity of encoding modules for H.264, and then we re-allocate the reference frame from L3 DDR-RAM to L2 SRAM to increase the speed of execution of ME module and re-allocate the function of consuming module from L3 DDR-RAM to L1 SRAM. Finally, we make use of direct memory access (DMA) and the default function of ADSP-BF548 to carry out program steps. Moreover, we also adopt the fast inter mode decision algorithm (FIDMA) [23] based on the proposed HEMA method to further reduce the complexity of inter prediction module. Experimental results show that the proposed HEMA method can achieve an average time improving ratio (TIR) about 56% when compared with the directly embedded H.264 encoder in ADSP-BF548. In addition, an average time improving ratio (TIR) can further up to 84.7% when the FIDMA based on HEMA method. It is obvious that the proposed embedded H.264 video encoder based on HEMA can be directly applied to consumer video applications.

並列關鍵字

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參考文獻

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