可應用於H.264視訊解碼器之彈性記憶體架構設計與DSP實現

H.264 視訊標準廣泛使用於現今的行動多媒體產品，與先前視訊標準相比，H.264能夠在更低頻寬下提供更優質的視訊，但是由於H.264增加太多設計複雜度使得實作成本過高。若把H.264直接應用於記憶體容量有限的行動裝置，將很難達到即時的視訊應用。因此，對於在硬體實現H.264視訊標準，記憶體的管理就顯得相當重要。為了能在數位訊號處理器(digital signal processor: DSP)晶片實現H.264視訊解碼器，本論文提出一彈性記憶體架構(flexible memory assignment architecture: FMAA)設計，利用ADSP-BF548模擬板來實現嵌入式H.264視訊解碼器。論文先對H.264解碼器的模組進行複雜度分析，其中包含熵解碼(entropy decoding: ED)、反量化(inverse quantization: IQ)、反整數餘弦轉換(inverse integer cosine transform: IICT)、畫框內預測(intra frame prediction: IFP)、運動補償(motion compensation: MC)及去方塊濾波器(de-blocking filter: DF)等主要模組。從分析結果可發現DF模組佔整體解碼複雜度約30.34%、IFP/MC模組佔約40.90%、IQ/IICT模組佔約9.20%、ED模組佔約6.72%，而其它解碼模組佔約12.84 %。因為ADSP-BF548採用多階層的記憶體架構，可分成大小為196 KB且核心速度533 MHz之核心記憶體L1(SRAM)、128 KB且核心速度267 MHz之內部記憶體L2(SRAM)和64 MB且速度133 MHz之外部記憶體L3(DDR-RAM)。當直接於ADSP-BF548模擬板來實現H.264解碼器，高運算複雜度的DF、IFP和MC等模組的函式(function)會被配置在執行速度較慢的L3，反而將複雜度低的函式配置在L1，而內部記憶體L2則未配置任何模組，造成H.264解碼器在DSP實現時過於緩慢。為了能加速H.264解碼器在ADSP-BF548模擬板實現的速度，我們利用所提出之FMAA技術來改善記憶體配置的效能。從H.264視訊解碼流程中，可以發現DF、IPF及MC等模組在解碼時，需重複的讀取參考畫面作為解碼時的參數依據，所提FMAA首先將參考畫面從L3彈性配置到L2，減少畫面解碼時所需耗費的時間。另對於H.264的函式配置方面，所提FMAA將DF模組的loopFilter、ED模組vlc及IFP/MC模組prediction等運算量較高的函式，從L3有效率的配置到L1來加速運算速度。本論文所提FMAA根據H.264解碼器各模組之複雜度和規則性，進行記憶體的有效管理和彈性配置，達到大幅加速H.264解碼器時間。最後為了讓H.264解碼更為流暢，透過直接記憶體存取(direct memory access: DMA)功能，我們也設計一雙緩衝器組(buffer group: BG)，進而達到H.264視訊解碼與播放同步。由實驗結果可以得知，本論文將ADSP-BF548的記憶體進行彈性且有效的記憶體配置後，以影像大小QCIF為例，平均每張畫面的解碼時間，明顯比直接在ADSP-BF548模擬板實現H.264解碼器降低平均約114.6106 cycles，時間改善率(time improving ration)約達到85.7%。從實驗結果驗證，論文所提FMAA技術能大幅提升H.264解碼效能，適合應用在現今的消費性電子產品上。

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並列摘要

H.264 video standard has been widely adopted in mobile multimedia applications nowadays. When compared with previous video standards such as MPEG-2, the H.264 can provide better decoded video quality under lower bandwidth. However, there are many complexity functions result in higher cost to implement H.264. Moreover, it is very hard to real-time decode the H.264 file when directly applied in the microprocessor unit and DSP chip for mobile device. To realize an embedded fast H.264 decoder and player based on ADSP-BF548 processor, we propose flexible memory assignment architecture (FMAA) to efficiency control memory of ADSP-BF548. H.264 decoder mainly consists of some modules including entropy decoding (ED), inverse quantization (IQ), inverse integer cosine transform (IICT), intra frame prediction (IFP), motion compensation (MC) and de-blocking filter (DF). The most consuming processes of decoder are DF, IFP and IICT modules. To overcome the problem of real-time decoding, we deeply study the memory assignment of ADSP-BF548 and fully use the hardware structure of DSP core. ADSP-BF548 blackfin processor adopts a hierarchical structure of memory including 192 KB and 533 MHz internal cache L1 (SRAM), 128 KB and 267 MHz internal memory L2 (SRAM) and 64 MB and 133 MHz external memory L3 (DDR-RAM). Since the high complexity DF、IFP and MC modules are assigned to L3 when directly embedded H.264 decoder based on ADSP-BF548, the decoding speed of H.264 is very low. In order to further accelerate H.264 decoder, we use FMAA to improve the efficiency of memory. In the study of H.264 decoding procedure, we find that the decoding modules of DF, IPF and MC need read reference frame to obtain the decoding parameter. To reduce the decoding time, the proposed FMAA assigns the reference frame from L3 to L2. Furthermore, we further move the program functions of DF, IPF and MC from L3 to L1. In addition, we use two buffer groups (BG) as parallel decoding mechanism of broadcast transformation. And, we make use of direct memory access (DMA) to carry out program steps. Experimental results demonstrate that the proposed FMAA can efficiently decode a QCIF video which reduces approximately 114.6106 MHz core cycles per frame and time improving ratio (TIR) about 85.7% when compared the directly H.264 video decoder system embedded in ADSP-BF548.

並列關鍵字

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參考文獻

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可應用於H.264視訊解碼器之彈性記憶體架構設計與DSP實現

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