AES之嵌入式處理器設計

DESIGN OF AN EMBEDDED PROCESSOR FOR ADVANCED ENCRYPTION STANDARD

賈證主(Chung-Chu Chia)

指導教授 ： 汪順祥

大同大學/電機資訊學院/通訊工程研究所/碩士(2005年)

摘要

AES演算法在未來三十年內將是對稱式加解密演算法的主流，一般以平行架構實現AES演算法的晶片，它的運算速度是相當快的，但比較耗費硬體的資源，且功能比較沒有彈性，只能完成加密及解密的工作。如果能夠使用一個微處理器來完成AES的運算，將會結省許多硬體的資源，且微處理器還可以勝任加解密之外的其它工作，其中的變化完全在於程式的操控，在應用上會變得非常有彈性，但它的速度是不如專司AES加解密晶片的。許多論文提出了加速微處理器實現AES演算法的方式，但大都是在程式的撰寫上作改進，本篇論文則提出了一個新的嵌入式微處理器軟核，它可以使用最少的程式碼並且有效的提升微處理器執行AES演算法的效能。
一般微處理器的ALU中是不包含有與AES相關之函數功能的，要使用它們來完成AES的加密及解密運算時，需要使用相當多的指令來完成，它會影響程式執行的效能且相當佔用程式記憶體的空間。本篇論文所設計的8bit-RISC微處理器AESMPU，特別將AES的模數乘法運算及位元取代運算納入ALU中，因此AESMPU的ALU除了能完成一般的算術邏輯運算外，還可以完成AES的函數運算，這樣的設計概念有助於提升以嵌入式處理器來實現AES的效能。

關鍵字

處理器 ； 先進資料加密標準 ； 嵌入式

並列摘要

AES will be the leading algorithm for symmetric encryption and decryption system in the coming thirty years. The speed to accomplish AES algorithm is quite fast when using a parallel architecture. But it costs much more hardware resources and its function is not flexible. If we use a microprocessor to accomplish AES algorithm, it will save more hardware resources and the processor can also accomplish another tasks beside encryption and decryption. In this way, it will become more flexible in application. But its speed still can not be compared with the chip which is designed only for AES. Many thesises try to improve the shortage in speed by some improvements in assembly language programming. This thesis proposes a new architecture of microprocessor designed in embedded soft core which will upgrades the speed to accomplish AES algorithm in an efficient way with shortest code length.
The ALU in a general microprocessor doesn’t have any functions related to AES, so it costs much more code length to accomplish AES encryption and decryption algorithm. This will directly downgrade the efficiency in processing AES algorithm with a longer code length which occupies program memory so much. In this thesis, we designed a 8-bit RISC embedded processor named AESMPU which includes AES functions in its ALU such as modular multiplication, byte substitution and inverse byte substitution. Thus, AESMPU can not only perform general ALU functions but also accomplish AES functions in a machine cycle. This will efficiently upgrade the processing speed in executing AES encryption and decryption when using an embedded processor.

並列關鍵字

AES ； Embedded ； Processor

參考文獻

[1] FIPS Publication 197, “Advanced Encryption Standard (AES)”, U.S. DoC/NIST, November 26, 2001.

[3] Kai Schramm and Christof Paar, “Implementation of the Advanced Encryption Standard(AES) on a Smart Card”, IEEE International Conference on Information Technology, vol. 1, pp.176-180, April, 2004.

[5] M. McLoone and J.V. McCanny, “Rijndael FPGA Implementation Utilizing Look-up Tables”, IEEE Workshop on Signal Processing Systems, pp. 349-360, September 2001.

[6] C.C. Lu and S. Y. Tseng, “Integrated Design of AES(Advanced Encryption Standard) Encrypter and Decrypter”, IEEE International Conference on Application-Specific Systems, pp. 277-285, July 2002.

[7] Nationanl Institute of Standard and Technology, “Recommendation for Block cipher modes of operation”, December 2001.