高速AES-OCB演算法架構的實現

IMPLEMENTATION OF HIGH SPEED ARCHITECTURE FOR AES-OCB ALGORITHM

林佑杰(Yu-Chieh Lin)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2009年)

摘要

摘要

在許多安全服務的應用中，Advanced Encryption Standard (AES) 加密演算法都是首選的演算法。在本論文中，我們用Xilinx公司的研發工具和Virtex-4 XC4VLX60-10ff1148 FPGA電路板實現了一個高速、十階管線式的AES-OCB加密電路。在IEEE 802.11中定義了以AES為基礎的加密系統，其中一種就運作在OCB模式。在這顆晶片中所有的模組都是用Verilog硬體描述語言來敘述。發展出來的AES-OCB晶片著重於提供高速度和確實的安全加密系統。這顆晶片的資料可以運作在時脈98MHz並且throughput可以達到1573 Mbits/sec。本篇論文也提供了類似的實現電路的效能比較。

關鍵字

高級加密標準 ； 補償暗碼

並列摘要

ABSTRACT

The Advanced Encryption Standard (AES) algorithm has become the default choice for many security services in numerous applications. In this thesis, we propose a high speed, 10-pipelined FPGA implementation of the AES-OCB (Offset Codebook) cipher using Xilinx development tools and Virtex-4 XC4VLX60-10ff1148 FPGA circuits. IEEE 802.11 defines the AES-based cipher system, one of them is operated on OCB mode. All the modules in this chip are described by using Verilog language. The developed AES-OCB chip is aimed at providing high speed with sufficient security. The operation data path operates at 98MHz resulting in a throughput of 1573 Mbits/sec. A comparison is provided between our design and similar existing implementations.

並列關鍵字

AES ； OCB

參考文獻

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