管線化AES-OCB演算法設計與實現

DESIGN AND IMPLEMENTATION OF PIPELINED AES-OCB ALGORITHM

李瑋騰(Wei-Teng Li)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2010年)

摘要

本論文首先介紹了Rijndael的數學理論，以及AES和OCB的原理介紹。在本論文中，設計了一個高速、五階管線式的AES-OCB加解密演算法。在這顆晶片中所有的模組都是用Verilog硬體描述語言來敘述，並利用ModelSim來模擬。這顆晶片的資料可以運作在時脈100 MHz並且資料處理量可以達到1066.67 Mbits/sec。

關鍵字

管線化

並列摘要

In this thesis, we introduce the Rijndael mathematical preliminaries. We also introduce the AES and OCB mode algorithm. In the thesis, which designed a high speed, 5-stage pipelined AES-OCB cipher. All of the modules in this chip are described by using Verilog language and used ModelSim to simulate it. The operation data path operates at 100 MHz resulting in a data throughput of 1066.67 Mbits/sec.

並列關鍵字

AES-OCB ； pipelined

參考文獻

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