週邊匯流排介面之系統整合晶片平台之設計

摘要本論文主要的是要建立一個通用且基本的平台作為將來SoC應用之研發,其中包含三個主要的內接匯流排: PCI 匯流排, Wishbone 匯流排及微處理器匯流排, 以及另外的一些共用的緩衝器, 例如雙埠記憶體, 先進先出暫存器, 及一些時序機, 以及LCD 介面之UART接口. 其中PCI 匯流排是一個位址線與數據線共用的高效率之32位元或64位元的匯流排, 是要用作為高整合週邊控制零件週邊介面卡以及處理器/系統間的內接結構. 作為可移動式IP核心的Wishbone系統整合晶片內接架框, 是一個用作為半導體IP核心高彈性設計的方法. 其目的是要減少SoC整合問題以促進設計的再使用. 這是靠在IP核心之間創造一共用介面來達成的. 而微處理器部分是選擇一個非常受歡迎且常用的8051微控制器. 這是一個位元的微處理器IP, 其中整合了時序控制器指令集內接記憶體及通用暫存器等. 整合了以上IP以及雙埠記憶體, 先進先出暫存器, 時序機及UART 等, 就行成一個通用的SoC 平台, 很容易在受歡迎的SoC 領域取得相關設計並在PCI 或 Wishbone 匯流排上做擴充. 這將是一個可擴充與廣大應用且低價位的平台.

關鍵字

週邊匯流排、系統整合晶片

並列摘要

ABSTRACT This thesis proposed a general purpose and basic platform for the SoC investigation in the future which includes three major interconnect bus : the PCI bus, the Wishbone bus and the Microprocessor bus, also consists some other common buffers such as dual port memory, FIFOs and some state machines, and UART port as a LCD interface. The PCI Local bus is a high performance 32-bit or 64-bit bus with multiplexed address and data lines, which is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in-cards and processor/memory systems. The WISHBONE System-on-Chip (SoC) interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. Wishbone is public domain standard. The microprocessor is selected with a very popular and common used 8051 micro-controller. It’s a 8-bit microprocessor IP, and integrate with sequencer, instructions set, internal memory, general purpose registers etc. Combine the IPs above and some dual port memory, FIFOs and UART, it becomes a general purpose SoC platform and easy to extend with PCI or Wishbone bus which are popular in the current SoC design field.