多層電路板電源層電磁干擾之防止策略

STRATEGY OF EMI REDUCTION FOR POWER/ GROUND PLANES IN MULTI-LAYER PCB DESIGN

柏斯順(Szu-shun Pai)

指導教授 ： 黃啟芳

大同大學/電機資訊學院/電機工程學系所/碩士(2007年)

摘要

現今資訊產品功能日益強大，國際品牌大廠對EMI的要求越發嚴謹。從原本只需符合FCC、CE規格要求，逐步要求under 3dB limit 甚至於要求到 under 6dB limit，對ODM 廠控制成本品質是一大考驗。
EMI一般以layout 手法降低雜訊以求符合規格，但是要under 6dB是非常不容易，甚至要增加極高的成本，在clock雜訊源上加RC 濾波電路要under 6 dB也是非常的困難的。即使符合under 6dB的要求，也可能出現以下的問題：是否影響產品功能？如果加金屬罩遮蔽雜訊，勢必大幅增加成本，且有可能影響散熱？因此本論文以Power Integrity 及layout 手法，試圖兼顧成本及品質以符合under 6dB limit要求.
我們採用實際的案例，在本文中以不同的思考模式及手法技巧加以實驗。Power Integrity 是一個非常複雜及難以分析的課題，因為影響參數太多，在目前高速電路板分析軟體對Power Integrity 應用有所限制，我們運用軟硬體設備相輔相成來解決問題。

關鍵字

多層電路板 ； 電磁干擾

並列摘要

In the recent years, all famous IT companies aim at EMI requirements more and more strict quality, from meeting limit to -3 db then -6dB step by step. Generally EMI solutions are in the clock trace with R/C or added metal enclosure, if we don’t raise the cost and don’t influent the quality in the EMI countermeasure. It is very difficult to meet FCC part 15 class B or EN55022 Class B radiation requirement under 6dB limit.
The Power Delivery System is generally considered quite complex and not easy to analyze, but all the circuits is related to it. This thesis gives different thinking direction to ensure power quality or integrity to be the first importance. On purpose is to lower power noise, increase operational range, and decrease noise.
The present high-speed PCB analytic software has its applied limit, so to control the most important influential factor and characteristics will help us analyze and design.
If we can notice the issue of multi-layer PCB stack up and power integrity at the design stage, we can solve this problem in the beginning, the developing time will be shortened as well as the times of changing layout will be decreased for the current procedure of product development. We will introduce EMI solutions for multi-layer PCB stack-up and use Power Integrity to decrease EMI of VoIP (voice over IP) products.
In this thesis we study a practical EMI case and use the layout skill to reduce 6dB radiated emission. Namely, it decreases one half energy of radiating disturbance.

並列關鍵字

multi-layer PCB ； EMI

參考文獻

[1] FCC part 15, Code of Federal Regulations Telecommunications 47; USA, 2001.

[2] “Limits and methods of measurement of radio interference characteristics of information technology equipment”, EN 55022, 1998(3rd edition).

[4] Guide for construction of Open Area Test Sites for Performing Radiated Emission Measurements, ANSI C63.7-1988.

[9] M. I. Montrose, EMC and the Printed Circuit Board Design, Theory and layout Made Simple, IEEE Electromagnetic Compatibility Society, 1999.

[11] W. Cui, M. Li, X. Luo, J. L. Drewniak, T. H. Hubing, T. P. VanDoren, and R. E. DuBroff, “Anticipating EMI From Coupling Between High-Speed Digital and I/O Lines,” IEEE 1999, pp.189-194.