適用於管道式快速富利葉轉換之低功率固定長度乘法器設計

DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS

吳韋志(Wei-jr Wu)

指導教授 ： 汪順祥

大同大學/電機資訊學院/通訊工程研究所/碩士(2008年)

摘要

本論文首先介紹快速傅立葉演算法，接著介紹兩種列越過和行越過的固定長度乘法器。我們所提出的固定長度乘法器是包含先前提出的列越過以及行越過乘法器之特色，並將其結合，已達到低功率的效果。本篇論文提出無號數列與行跨越固定長度乘法器、有號數列與行跨越固定長度乘法器、有號數列與行跨越CSD固定長度乘法器三種設計並適用於快速富利葉轉換處理器。設計的實現是使用UMC 0.35μ 2P4M CMOS製程，無號數列與行跨越固定長度乘法器與有號數列與行跨越固定長度乘法器分別可達到節省13%及6%的功率消耗，並可將其特色應用於快速富利葉轉換處理器中達到降低功率消耗。

關鍵字

快速富利葉轉換 ； 乘法器

並列摘要

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the unsigned row-and-column-bypassing structure or two’s-complement row-and-column-bypassing structure or row-and-column- bypassing CSD structure, the columns and rows are passed and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35mμ 2P4M CMOS process. Simulation results show that our two methods has 13% and 6% power reduction when supply voltage is 3.3V. We have used our methodology to design a low-power parallel multiplier for the 64-point Fast Fourier Transform processor. Simulation results show that our approach can result in significant power savings over conventional multipliers.

並列關鍵字

multiplier ； FFT

參考文獻

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