改良式可變長度快速傅立葉轉換處理器

IMPROVED ARCHITECTURE OF FAST FOURIER TRANSFORM PROCESSOR

郭德威(Wei-de Kuo)

指導教授 ： 蔡明傑

大同大學/電機資訊學院/電機工程學系所/碩士(2008年)

摘要

本論文是採用Single-path Delay Feedback 架構來完成一種適用於正交分頻多工通訊系統可變長度的傅立葉處理器並且採用一種新穎的演算法radix-2/4/8/16來完成我們的設計。為了規則性及低複雜度，我們使用了Radix-2/4/8/16演算法來有效的減少複數乘法而，並且也容易以VLSI實現，特別是在管線架構的實現上，此外，我們提出的快速傅立葉處理器是應用於IEEE 802.16 (WiMAX)。
我們介紹幾種快速傅立葉轉換演算法，為了能實現更多不同長度，需要能夠用在所有2的冪次方點數的快速傅立葉轉換系統上，其中mixed-radix 4/2 除了演算法可產生有規律性的硬體結構外，效率也比radix-2 好，所以選擇了mixed-radix 4/2來提昇其對不同長度的適應性與簡易度，並且此傅立葉快速處理器以Verilog硬體語言描述設計及ModelSim和Xilinx ISE模擬其結果。

關鍵字

可變長度. 2/4/8/16 ； 快速傅立葉轉換 ； WiMAX

並列摘要

In this thesis, the proposed design adopts SDF architecture. Moreover, we propose a new variable-length FFT processor with a novel algorithm, radix-2/4/8/16, for OFDM communication system. Due to the regularity and lowest hardware circuit complexity, radix-2/4/8/16 can efficiently minimize the number of complex multiplications and be implemented in VLSI design, especially in pipeline-based architecture. The proposed FFT processor can be used for the required length of IEEE 802.16 (WiMAX) standard.
We have introduced some FFT algorithms. Due to implement more different length, we need a algorithm that can suit all 2n-point systems. In contrast, mixed-radix 4/2 FFT algorithm is capable of producing hardware with structure regularity, and it is more efficient than radix-2 FFT algorithm. It is therefore selected for improving adaptability and facilitation, and this FFT processor has been implemented by using VerilogHDL, ModelSim and Xilinx ISE for circuit design and simulation, respectively.

並列關鍵字

2/4/8/16 ； variable-length ； fft ； WiMAX

參考文獻

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