8位元50MHZ取樣頻率之CMOS管線類比數位轉換器

在現今許多的應用當中，大多使用數位訊號處理技術來處理所傳輸的資料，因此，在接收到的類比訊號級數位訊號處理系統間，就需要將類比訊號轉換成數位訊號的介面。由於近年來無線通訊系統和個人可攜式電子產品的成長，對於低功率的電路也有著不可或缺的需求。在許多種類的CMOS類比數位轉換器的架構中，由於管線式類比數位轉換器每一級的取樣保持電路如同快閃式類比數位轉換器一樣能同時動作，因此管線式類比數位轉換能達到高速的輸入性能和快速的處理能力。在本篇論文中，針對高速度的管線式類比數位轉換器做設計，並且在設計過程中盡可能的減低消耗功率。在本篇論文中，使用了台積電0.18微米互補式金氧半製程設計與實現一個八位元，50MHz 取樣頻率的 CMOS 管線式類比數位轉換器，每一個階段為1.5 位元的解析度。根據模擬結果，整體電路在50 MHz 的取樣頻率下 SNR 為 48.81 dB，可達7.81位元的精確度，功率消耗為 105 mW。

關鍵字

管線式；類比數位轉換器

並列摘要

Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and DSP system and portable consumer electronics, the demand for low-power integrated circuits is indispensable. In many types of CMOS analog to digital converter (ADC) architectures, a pipelined architecture can archive good dynamic range performances and the same throughput as the flash ADC due to the pipelined operation in each range. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipations as well. In this thesis, an 8-bit 50MHz pipelined A/D converter, with 1.5-bit resolution per stage, has been successfully designed and implemented using the TSMC 0.18μm 1P6M CMOS process. Simulation results show that the designed pipelined ADC can operate at 50MHz with 48.84dB signal- to- noise ratio – conforming to the 7.81-bit accuracy, and the estimated power dissipation is about 105 mw.

並列關鍵字

Pipeline ； ADC

參考文獻

[1] R. Jacob Baker,"CMOS Mixed-Signal Circuit Design," John Wiley & Sons, Boston, June. 2002.

[4] T. Cho and P. R. Gray, "A 10 b, 20 Msamples/s, 35mW Pipeline A/D Converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.

[6] Kush Gulati and Hae-Seung Lee, "A High-Swing CMOS Telescopic Operational Amplifier," IEEE J. Solid-State Circuits, vol.33, no. 12, pp. 2010-2019, Dec. 1998.

[7] Zong-Xian Lv, "Design of a Pipelined Analog to Digital Converter for IEEE 802.11a WLAN," Master Thesis, National Chung Hua University, July. 2004.

[8] Chin-Hsun Chen, " Oversampling with Second-Order Sigma-Delta Modulator," Master Thesis, National United University, June. 2006.

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8位元50MHZ取樣頻率之CMOS管線類比數位轉換器

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