整合自時硬體加速器到Nios II平台

Integrating Self-timed Hardware Accelerators into Nios II Platform

黃俊凱(Chun-Kai Huang)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2009年)

摘要

當嵌入式系統在應用上有增進效能的需求，即會採用硬體來加速以往採用處理器執行的某些關鍵工作，然而硬體電路的設計趨勢以同步電路為主，相對的非同步電路設計複雜且可用的IP模組較少。
本篇論文提出一種新的硬體加速器設計方法，利用本實驗室開發的SoCAD工具從C++或Java等高階語言的程式碼，自動產生可重複使用的自時硬體模組，結合同步電路到非同步電路溝通介面成為自時(Self-timed)硬體加速器(Hardware accelerator)，整合到Nios II平台使用。此自時硬體加速器可取代並加速Nios II處理器的軟體部份達到Time to Market目的，並兼具非同步電路的低功耗、省電、速度快、可重用的優點。
我們使用GCD(Greatest Common Divisor)、Summation和RSA演算法為範例，測試並比較軟體、C2H硬體加速器、以及自時硬體加速器所佔用的邏輯數量和執行時間。實驗數據的結果顯示本方法比沒有/有C2H硬體加速器的Nios II平台快，以GCD為例約快1.4/1.5倍，以Summation為例沒有管線設計約快8.0/1.3倍，有管線設計約快12.3/2.1倍，以RSA為例約快1.1/20.7倍。

關鍵字

非同步電路 ； 自時系統 ； SOPC ； Nios II ； 硬體加速器

並列摘要

Hardware accelerators are commonly used to speed up some critical operations in embedded system design.
This thesis proposes a new approach to design hardware accelerator which integrates self-timed hardware accelerators into Altera Nios II platform. The self-timed hardware accelerator consists of one self-timed core which is automatically synthesized from C++ or Java specification by using SoCAD tool and a synchronous to asynchronous interface to plug in the self-timed core to Avalon bus of Nios II SoPC platform.
GCD、Summation and RSA are used as examples to carry out the performance evaluation. The experimental results shows that our self-timed hardware accelerator is 1.4/1.5 times, 8.0/1.3 times, 12.3/2.1 times, 20.7/1.1 times faster than Nios II platform without/with C2H hardware accelerator in GCD, non-pipeline Summation, pipeline Summation and RSA examples, respectively.

並列關鍵字

Asynchronous circuit ； Self-timed system ； SOPC ； Nios II ； Hardware accelerator

參考文獻

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[9] Altera Corp., “Avalon-MM Interface Specification Version 1.2”, April 2009.

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