迅速整合可重複使用的Balsa IPs到Nios II客製化指令

Rapid integration of reusable Balsa IPs to the Nios II custom instruction

陳胤宇(Yin-Yu Chen)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2010年)

摘要

當嵌入式系統有增進效能需求的時候，往往會使用硬體加速器(Hardware accelerator)來加速處理器執行的關鍵工作。硬體加速器設計上目前仍以同步電路為主，非同步電路雖具有種種優點，但因電路設計複雜，所以用於硬體加速器上則較少。
在設計Nios II Custom Instruction中，要先使用硬體描述語言來設計硬體加速器，還需了解Nios II Custom Instruction的協定並設計此介面，接著硬體加速器透過SOPC Builder工具加進到Custom Instruction中，整個實作過程相當的耗時繁瑣。本篇論文提出一種新的方法迅速整合Balsa硬體到Nios II Custom Instruction的設計，利用Manchester大學所開發的Balsa工具產生可重複使用的非同步硬體，並且設計同步電路到非同步電路溝通介面，快速整合到Nios II平台使用，達到縮短design Time目的。此非同步硬體加速器除了具有低功耗、省電、速度快、可重用的優點外，還可取代Nios II處理器的軟體部份，並加速執行的速度。
測試執行速度上，範例有GCD、Summation、RSA和浮點數乘法運算，並與軟體和Altera C2H做比較。由實驗數據可得知，此論文比軟體和C2H加速器還快，以GCD為例比軟體快13.8倍，比C2H快7.3倍；Summation則是比軟體快13.7倍，比C2H快5.7倍；RSA則是比軟體快12.0倍，比C2H快1.7倍；浮點數乘法運算比軟體快12.0倍，比C2H快1.7倍。

關鍵字

SOPC ； Nios ； 硬體加速器 ； Balsa

並列摘要

This paper proposes a new approach to integrate Balsa accelerators into Nios II custom instruction. We first generate reusable Asynchronous hardware modules from Balsa tool and design a synchronous to asynchronous interface, and finally integrate the Asynchronous hardware accelerator into Nios II custom instruction. Our Balsa accelerator is used to replace and accelerate the corresponding software part of Nios II processor for reduce design time applications and has the advantages of low power consumption and reusability.
GCD、Summation、RSA and Float Multiplication are exploited to test and compare our asynchronous accelerator with C2H accelerator. Experiment results show that our accelerator is 7.3, 5.7, 1.7, 1.7 times faster than the Nios II platform with C2H accelerator with GCD, Summation, RSA and Float Multiplication examples, respectively.

並列關鍵字

Nios ； SOPC ； Balsa ； Hardware Accelerator

參考文獻

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[12]黃俊凱、鄭福炯、陳胤宇, "整合自時硬體加速器到Nios II平台," 2009資訊科技與應用產學研討會, 大同大學