合成SystemC程式到同步電路

隨著科技的進步，對於SOC(System On a Chip)產品功能的要求也隨著提高。產品所期望提供的功能趨於複雜，在開發的時程上也必須花費更多的時間來進行設計，一般舊有以Gate Level來進行設計需耗費龐大的時間，已經不適合用於複雜的功能設計。是以現今的設計方法大多改以High Level的方式進行設計，以更接近人類的思考方式來進行設計，可以減少花費大量的時間於設計上，降低開發所需的成本，並加快產品上市的時間。而SystemC是一種高階語法，除了擁有前面所提到的High Level Synthesis的優點，更可以同時描述軟體及硬體的行為，減少了在軟硬體整合上可能發生錯誤的機率。因此在以SystemC進行開發設計後，直接利用SOCAD合成工具將高階程式轉換成對應的同步電路，避免使設計者以gate level的思維進行設計，進而大大的縮短整體開發所需的時程。

關鍵字

SystemC ；有限狀態機；高階合成

並列摘要

The design complexity to build SOC (System On a Chip) products is increasing and becoming more complex with the advance in technology. One promising way to solve the design complexity or productivity gap is high-level synthesis. SystemC is the IEEE standard to support high-level synthesis. This thesis proposes an efficient method to translate SystemC programs into synchronous sequential circuits based on a graph notation. In particular, the SystemC programs are translate into a set of sub-graphs. Each sub-graph corresponds to a state in finite state machine. The sub-graphs are then translated into VHDL codes which are verified in Altera Quartus tool. The experimental results show that the circuits synthesized by our translation methodology have the low worst case delay and have larger number of states.

並列關鍵字

Finite State Mach ； High level synthesis ； SystemC

參考文獻

[2] Andreas Gerstlauer and Daniel D. Gajsk, “System-level abstraction semantics,” 15th International Symposium on System Synthesis, pages 231-236, 2002

[11] Open SystemC Initiative. “ SystemC Synthesizable Subset 1.3 draft,” 2009

[12] Ping-Yun Wang, “Design and Implementation of Asynchronous Java Processor,” Tatung, 2004

[13] Preeti Ranjan Panda, "SystemC - a modeling platform supporting multiple design abstractions," presented at System Synthesis, The 14th International Symposium, 2001.

[18] W. Rhett Davis, "Getting high-performance silicon from system-level design," Annual symposium on VLSI, 2003. IEEE Computer Society, pages 238-243, 2003.

國際替代計量

合成SystemC程式到同步電路

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