全數位鎖相迴路設計

DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS

張弘儒(Hung-ju Chang)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2012年)

摘要

本論文所提出的全數位鎖相迴路(ADPLL)電路架構包含相位頻率偵測器、數位時間轉換器、遞迴式迴路濾波器、數位控制振盪器、緩衝器以及除頻器。本論文提供一個新修正的數位時間轉換器架構，可輕易的將所有的輸入脈波轉換成二進制的數位字串訊號表示，並且修正了BUF的內部架構，使得鎖相迴路的所有的電路動作正常運作不受訊號延遲干擾。最後經由模擬結果得知數位控制振盪器的鎖定頻率誤差值範圍由-0.68%到1.62%。本論文輸出的操作頻率為152~581MHz。論文中使用Xilinx Spartan3E XC3S1600E-5FG320 與MODELSIM PE 10.1a 以及ISE 10.1 來驗證新修正的數位時間轉換器和BUF 與所有架構之可行性。

關鍵字

ADPLL ； 全數位鎖相迴路 ； 數位時間轉換器

並列摘要

In this thesis, we designed an all digital phase locked loop (ADPLL). Its structures included phase frequency detectors, time to digital converter, loop filter, digital controlled oscillators, buffer and divider. This thesis not only proposed a new modified time to digital converter which can transform all the impulse into a digital string signal but also modified the circuits of buffer which make all the circuits work well and without interfering of signal delay. Finally, we know that the ranges of locking frequency error are -0.68%~1.62%. The output frequency ranges are 152~581MHz. In this thesis, we use Xilinx Spartan3E XC3S1600E-5FG320, MODELSIM PE 10.1a and ISE 10.1 to check new modified time to digital converter, BUF and all other circuits.

並列關鍵字

time to digital converter ； ADPLL ； all digital phase locked loop

參考文獻

[1] Chung-Cheng Wang, “A digital frequency synthesizer HDL generator for

locked loop (ADPLL) based clock recovery circuit,” IEEE Journal of

3rd ed., McGraw-Hill, New York 1997.

[5] Terng-Yin Hsu, “The study of all digital phase locked loop (ADPLL) and

[6] 王嘉斌, “All Digital Frequency Synthesizers, ” Master Thesis, 大同大