Modern technology is advancing rapidly, and development of semiconductor process makes devices have lower power and smaller area, optimized shortest path length of the connecting elements. For this purpose, macro and standard-cells floorplan play an important role. In this paper, we present a new algorithm for macro placement to handle wirelength and macro placement area. By re-classify all macros and program floating border value, we improves wirelength and the placement area size flexibly. Experimental results show that we can improve the performance effectively by integrating our macro placer with some standard-cell placers, such as NTUplace3, NTUplace4, to minimize the macro placement area size and shorten the distance between elements simultaneously.