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Software/Hardware Co-Simulation of Detection of Integer Frequency Offset and Cell Identity for FDD-LTE Downlink

下鏈路FDD-LTE之整數頻率偏移及細胞索引偵測之軟硬體相互模擬

摘要


In this paper, we implement the integer carrier frequency offset (ICFO) and cell identity (CID) detectors for the FDD-LTE downlink system. We adopt MATLAB/System-Generator co-simulation method for facilitating hardware implementation. Besides, a full-precision approach is employed for achieving the same detection performance as that of the software simulation. In the design, phase-difference sample (PDS) algorithms are chosen to compensate the channel effects [5], [7]. First, the joint detection algorithm of ICFO and sector CID is realized by using the PDSs of received primary synchronization signal (PSS) [5]. Next, the group CID detector is implemented by using the PDSs of received secondary SS (SSS) [7]. The whole detector architecture is then proposed, including signal-control circuit, a bank of parallel cascaded correlators (PCCs), and the 32-order comparator. Finally, we compare the System Generator output results and MATLAB simulation results to verify the validity of the proposed hardware architecture.

並列摘要


在本文,我們實現了下鏈路分頻雙工-長期演進(Frequency-Division-Duplex-Long -Term-Evolution, FDD-LTE)系統的整數頻率偏移(Integer Carrier Frequency Offset, ICFO)和扇形細胞索引(Sector Cell Identity, Sector CID)偵測器。本文採用MATLAB /System Generator 相互模擬的硬體實現方法,並採用全精確度的方法以維持軟體模擬的偵測性能。在設計中,選擇相位差取樣(Phase-Difference Samples, PDS)的演算法以補償通道效應[5],[7]。首先,利用接收到的主要同步訊號(Primary Synchronization Signal, PSS)產生PDS 用以實現ICFO 和Sector CID 的聯合偵測器演算法[5]。接著,利用接收到的次要同步訊號(Secondary Synchronization Signal, SSS)構成PDS 以實現分群細胞識別碼(Group CID)偵測器[7]。我們提出整體偵測器架構,包含信號控制電路,平形式串聯相關器(PCCS)以及32 階比較器。最後,我們比較System Generator 的輸出結果和MATLAB 模擬結果以驗證硬體架構的有效性。

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