本論文主要以有限脈衝響應(finite impulse response, FIR)濾波器架構實現分頻雙工長期演進(frequency-division-duplex-long-term-evolution, FDD-LTE)系統之細胞搜尋估測器,以降低整體電路的複雜度。本論文實現了整數頻率偏移(integer frequency offset, ICFO)偵測器、扇形細胞索引(Sector Cell Identity, Sector CID)偵測器以及分群細胞識別碼(Group Cell Identity, Group CID)偵測器。為了快速雛形化我們的硬體設計,我們採用MATLAB 的軟體與Xilinx之System Generator的電路設計工具,進行軟、硬體相互驗證。 首先,我們利用頻域式相位差序列導入帶有事先運算好的主要同步相關訊號的FIR濾波器架構,以計算出ICFO與Sector CID之聯合價值函數值。接著我們設計出比較器模組找出最佳價值函數偵測值與其相對應之索引值。第二,在實現Group CID偵測器,我們利用接收端之次要同步訊號(Secondary Synchronization Signals, SSS)輸入帶有事先預算之不同的初始序列之FIR濾波架構以串列式方式得到偵測結果,接著並利用比較器模組找出正確的價值函數最大值與其相對應之索引值。最後,我們將硬體模擬結果與MATLAB之軟體模擬對應比較,驗證兩者模擬結果十分一致,達到電路實現的效度。
This thesis primarily focuses on using the finite-impulse response (FIR) architecture to implement the low-complexity cell search estimator for the downlink frequency-division-duplex long-term evolution (FDD-LTE) system. This thesis implements the integer carrier frequency offset (ICFO) detector, the sector cell identity (Sector CID) detector, and the group cell identity (Group CID) detector. For rapid prototyping, we employ both the MATLAB software and System Generator of the Xilinx for software and hardware co-simulation. First, we use the phase-difference samples of the adjacent carrier frequencies and pass them into the FIR filter with the pre-calculated coefficients about the primary synchronization signals (PSS) to compute the values of the cost function of the ICFO and Sector CID. Then, the comparator module is designed to find the optimal detection value of the cost function and its corresponding index. Next, as for detecting a Group CID, we use the receiver secondary synchronization signals (SSS) to pass through the FIR structure with different initial filter coefficients to obtain the detection results. Then, a comparator module is used to find the correct detection value and its corresponding Index. Finally, we use software and hardware co-simulation results for verifying the validity of our design.