序向二進位正整數乘法器之設計

The Design of Sequential Multiplier of Binary Positive Integers

謝金石 ； Kin-Shue Hsieh

《資訊縮影管理》 12期 (1989/03) Pp. 34-47

摘要

計算機中的算術邏輯單元在執行乘法運算時，若乘法係以邏輯排列的方法設計，雖然執行的速度較快，然而，由於其硬體所需較多，相形價格就會提高；此外，因傳輸延遲時間的增加，使得計算機的系統時脈頻率不能大快。因而便影響了整部計算執行的速度。
本論文的目的係設計一個乘法器，在一個週期執行一個位元的相乘，一個週期由二個時脈組成，第一個時脈執行加或者不加；第二個時脈執行右移。所持用之理論是二進位正整數乘的運算方法。即一般紙筆的算法。由於本論文只討論正整數範圍，故乘數和被乘數均須爲正整數，如果是n位元乘法器則乘數和被乘數的最大值是2(上標 n)-1，所得到之積是2n位元，最大值是2(上標 2n)-1。
在本論文係以四位乘法器做爲討論的範例。

並列摘要

If the multiplier is designed with the method of logic array, the arithmetic logic unit of the computer is quicker in the operation of multiplication. But, the multiplier designed with this method needs more hardware. The more the hardware, the higher the price. Besides, the propagation delay time being increasing, the frequency of the computer system clock can not be very quick. This will result in effecting the operation speed of the computer.
The object of this thesis is to design a multiplier, which operates one bit multiplication in a cycle. Every cycle consists of two pulses. The multiplier operates addition or no addition in the first pulse and operates shifting right in the second one. The theory used is the multiplication method of binary positive integers, i.e. the algorithm of paper-and-pencil multiplication in general condition. The thesis being discussing the scope of positive integers only, the multiplier end the multiplicand must be all positive integers. The maximum values of the multiplier end the multiplicand are all 2(superscript n)-1, if the multiplier is n-bit one. The product is 2n-bit and the maximum value of it is 2(superscript 2n)-1.
In the thesis, the 4-bit multiplier is used for the example of discussion.