56-Gb/s 不歸零碼接收器

56-Gb/s NRZ Receiver

蔡仲耘(Chung-Yun Tsai)

指導教授 ： 陳中平

共同指導教授 ： 彭朋瑞(Pen-Jui Peng)

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202200611

摘要

本論文旨在40nm CMOS中演示使用波特率時脈資料恢復電路的56-Gb/s NRZ接收器。
此架構可以共享資料決策和相位檢測的比較器，可以大幅度地減少比較器的數量並且降低晶片整體的功耗，內部電路包括可變增益放大器、連續時間等化器、一抽頭決斷反饋等化器、基於相位內插器之全數位時脈資料恢復電路。

關鍵字

可變增益放大器 ； 連續時間等化器 ； 決策反饋等化器 ； 波特率相位偵測器 ； 相位內插器 ； 全數位式時脈資料恢復器

並列摘要

The objective of this thesis is to demonstrate the application of baud-rate clock and data recovery in a 56-Gb/s NRZ receiver with TSMC standard digital 40nm CMOS technology.
This architecture can share data decision and phase detection comparators, greatly reduce the number of comparators, power consumption, the internal circuit , including variable gain amplifier, continuous time equalizer, one-tap decision feedback equalizer, and all digital clock data recovery circuit based on phase interpolator.

並列關鍵字

variable gain amplifier ； low frequency equalizer ； continuous time linear equalizer ； decision feedback equalizer ； baud rate phase detector ； all digital clock and data recovery

參考文獻

[1]T. Shibasaki et al., “A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 1–2.

[2]T. Shibasaki, et al., “A 56Gb/s NRZ electrical 247mW/lane serial link transceiver in 28nm CMOS”, ISSCC, pp. 64-65, Feb. 2016.

[3]P.A. Francese, et al., “A 50Gb/s 1.6pJ/b RX data-path with quarter-rate 3-tap speculative DFE”, IEEE Symp. VLSI Circuits, pp. 267-268, June 2018.

[4]D. Schinkel, et al., “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup and Hold Time,” ISSCC Dig. Tech. Papers, pp. 314–315, Feb. 2007.

[5]S. Parikh, et al., “A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS,” ISSCC Dig. Tech. Papers, pp. 28–29, Feb. 2013.