本研究首先探討通道層退火溫度，以及通道層沉積時的氧氣流量對於P型氧化錫薄膜電晶體的影響。通道層退火150oC時通道仍呈現金屬特性，而退火200oC後則顯示出有利於電晶體整流的半導體特性。此外，沉積氧化錫通道層時的氧氣流量越大有助於氧化錫晶粒成長，能夠提高元件的載子遷移率和驅動電流，但也因為晶粒增加使得漏電流增加，所以在沉積氧化錫時選擇合適的氧流量是很重要的。接著改變氧化錫通道層厚度，分別沉積6奈米、10奈米、15奈米的氧化錫通道層，其對應的載子遷移率分別為3.58 cm2V-1S-1、6.3 cm2V-1S-1、3.46 cm2V-1S-1，對應的開關電流比為1.58 x 103、9.55 x 10、6.21 x 10。由此現象我們可以了解到，通道層越厚通道層內的錫空缺就越多，導致電洞越多，且因為通道層厚度較厚，閘極控制能力下降，不足以排開電洞完全關閉元件。接著利用低溫氟電漿對氧化錫通道層進行改質，觀察氟電漿對氧化錫薄膜電晶體造成的影響。結果證實以氟電漿對通道層進行改質能夠改善氧化錫薄膜電晶體的漏電流。最後減薄氧化錫通道層厚度，並以退火溫度250oC、300oC、350oC進行通道層後退火，得到n型氧化錫薄膜電晶。本研究以通道層厚度6奈米為界線，當厚度大於6奈米之元件為p型氧化錫薄膜電晶體；當厚度小於6奈米之元件為n型氧化錫薄膜電晶體。

This study first explored the effects of channel annealing temperature and the oxygen flow rate at the channel layer on the P-type SnO-TFT. Channel annealing at 150°C still exhibits metal properties, while annealing at 200°C shows favorable semiconductor characteristics for transistor rectification. In addition, the larger oxygen flow rate when depositing the tin oxide channel layer contributes to the growth of the tin oxide grains, the carrier mobility and the driving current of the devices can be improved, but also because the crystal grains increase the leakage current. It is important to choose the right oxygen flow. Followed by deposition of 6 nm, 10 nm, 15 nm tin oxide as the channel layer, the corresponding mobility of their devices were 3.58cm2V-1S-1, 6.3cm2V-1S-1, 3.46cm2V-1S-1, and the corresponding Ion/Ioff current ratio is 1.58 x 103, 9.55 x 10, 6.21 x 10. From this phenomenon we can understand that the channel layer thicker the channel layer of tin vacancy is more, resulting in more holes, and because the channel layer thickness is thick, the gate control capacity decreased, not enough to discharge the hole completely closed devices. Then, the effect of the tin oxide channel layer on the tin oxide thin film transistor was modified by the low temperature fluorine plasma. As a result, it was confirmed that the modification of the channel layer with the fluorine plasma could improve the leakage current of the tin oxide thin film transistor. Finally, the thickness of the tin oxide channel layer was reduced and the channel layer was annealed at an annealing temperature of 250oC, 300oC and 350oC to obtain an n-type SnO-TFTs. In this study, the tin oxide thin film transistor with the channel layer thickness of 6 nm as the boundary, when the thickness of more than 6 nm devices for the p-type SnO-TFTs; when the thickness of less than 6 nm devices for the n-type SnO-TFTs.

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