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研究生: 邱宣策
Chiou, Shiuan-Tse
論文名稱: 十四位元三億取樣頻率之電流汲取式數位類比轉換器
A 14-bit 300 MHz Current-Steering Digital-to-Analog Converter
指導教授: 郭建宏
Kuo, Chien-Hung
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 72
中文關鍵詞: 電流式數位類比轉換器分段式架構
英文關鍵詞: Current-steering DAC, Segmented Architecture
DOI URL: http://doi.org/10.6345/THE.NTNU.DEE.006.2019.E08
論文種類: 學術論文
相關次數: 點閱:44下載:0
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  • 近年來,由於積體電路的製程發展迅速,促使著行動通訊發展越發茁壯,在第四代行動通訊已經盛行的現在,促成行動通訊裝置已經成為生活必需品。毫微微蜂巢式基地台(femtocell)的出現,增加了通訊信號的覆蓋率以維持良好的傳輸品質。為了構築一台能夠準確傳遞封包的毫微微蜂巢式基地台,一個高解析且高頻寬的數位類比轉換器的設計是很重要的。

    本篇論文使用電流汲取式數位類比轉換器來達成所需的十四位元解析度與三億赫茲取樣頻率,而此十四位元電流式數位類比轉換器採用分段式(Segmented)架構,此架構以兩塊六位元的溫度計碼(Thermometer-based)轉換器與二位元二進制碼(binary-weighted) 轉換器所組成。此電路採用台積電TSMC 0.18 μm 1P6M mixed-signal CMOS 製成完成,類比與數位的供應電源分別採用 1.8 V 與 1 V。電路量測結果,最大 SFDR 能夠達到 44.72 dB,而整體消耗功率為 23.52 mW。

    In the recent years, because the technology of integrated circuits develop rapidly, it improves the technique of mobility communication. Nowadays, the fourth generation of mobile communication has become popular, and mobile
    communication devices have become a necessity. The emergence of femtocells has increased the coverage of communication signals to maintain good transmission
    quality. In order to construct a femtocell base station capable of accurately transmitting packets, the design of a high resolution and high sample frequency digital-to-analog converter is very important.

    In this paper, a 14-bit 300MHz digital-to-analog converter is achieved by current-steering architecture, and this 14-bit circuit consists of three segments. Two of it is a 6-bit thermometer-based converter, and the other is a 2-bit binary-weighted converter. The supply voltage in analog and digital is applied in 1.8 V and 1 V, respectively. From the measurement results, a peak SFDR of 44.72 dB is achieved in TSMC 0.18μm 1P6M mixed-signal CMOS, and the power consumption is 23.52 mW.

    摘要 i ABSTRACT ii 誌謝 iii 目錄 iv 圖目錄 vii 表目錄 xi 第一章 緒論 1  1.1 研究動機與背景 1  1.2 積體電路設計流程 2  1.3 論文大綱與概要 3 第二章 數位類比轉換器的技術與架構 5  2.1 前言 5  2.2 理想數位類比轉換器與其性能參考目標 5   2.2.1 理想數位類比轉換器 5   2.2.2 數位類比轉換器的性能參考目標 6    2.2.2.1 靜態特徵 6    2.2.2.2 動態特徵 10  2.3 數位類比轉換器的架構 13   2.3.1 電壓調節式數位類比轉換器(Voltage-Scaling DAC) 13   2.3.2 電流調節式數位類比轉換器(Current-Scaling DAC) 14   2.3.3 電荷調節式數位類比轉換器(Charge-Scaling DAC) 18  2.4 章節結論 19 第三章 數位類比轉換器的非理想效應之探討 21  3.1 前言 21  3.2 電流源電晶體的隨機誤差 21  3.3 電流源電晶體的有限輸出阻抗(Finite Output Impedance)23  3.4 電流源電晶體的頻率響應 25  3.5 電流源開關電晶體的非理想效應 26  3.6 電流源陣列的不匹配效應 27   3.6.1 蝕刻速率變化(Etch Rate Variation) 27   3.6.2 梯度誤差(Gradient Mismatch) 28  3.7 現今發展 30  3.8 章節結論 32 第四章 數位類比轉換器的設計與實現 33  4.1 前言 33  4.2 十四位元數位類比轉換器之架構圖 34  4.3 輸入暫存器(Input Register) 35  4.4 行列式解碼器與電流源陣列(Row & Column Decoder & Current Matrix Control) 35  4.5 電流源電晶體之構成 38  4.6 偏壓電路(Bias Circuit) 40  4.7 數位類比轉換器的模擬結果 41  4.8 佈局規劃 44  4.9 晶片量測環境建置 50   4.9.1 供應電壓源的建立 51    4.9.1.1 類比供應電壓電路 51    4.9.1.2 數位供應電壓電路 52    4.9.1.3 濾波槽電路(Filter Tank) 52  4.10 量測結果 53  4.11 結果探討 57  4.12 章節結論 65 第五章 總結與未來展望 67  5.1 總結 67  5.2 未來展望 69 參考文獻 70 作者簡歷 72 學術成就 72

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